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i386: Clean up cache CPUID code

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Always initialize CPUCaches structs with cache information, even
if legacy_cache=true. Use different CPUCaches struct for
CPUID[2], CPUID[4], and the AMD CPUID leaves.

This will simplify a lot the logic inside cpu_x86_cpuid()

Backports commit a9f27ea9adc8c695197bd08f2e938ef7b4183f07 from qemu
This commit is contained in:
Eduardo Habkost 2018-06-15 11:44:41 -04:00 committed by Lioncash
parent 1a91edd263
commit 7837f23cd9
No known key found for this signature in database
GPG key ID: 4E3C3CC1031BA9C7
2 changed files with 116 additions and 111 deletions
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213
qemu/target/i386/cpu.c
View file

@ -1246,55 +1246,63 @@ struct X86CPUDefinition {
CPUCaches *cache_info; CPUCaches *cache_info;
}; };
static CPUCacheInfo epyc_l1d_cache = {
DCACHE,
1,
32 * KiB,
64,
8,
1,
64,
1,
1,
true,
};
static CPUCacheInfo epyc_l1i_cache = {
ICACHE,
1,
64 * KiB,
64,
4,
1,
256,
1,
1,
true,
};
static CPUCacheInfo epyc_l2_cache = {
UNIFIED_CACHE,
2,
512 * KiB,
64,
8,
1,
1024,
1,
};
static CPUCacheInfo epyc_l3_cache = {
UNIFIED_CACHE,
3,
8 * MiB,
64,
16,
1,
8192,
1,
true,
false,
true,
true,
};
static CPUCaches epyc_cache_info = { static CPUCaches epyc_cache_info = {
{ &epyc_l1d_cache,
DCACHE, &epyc_l1i_cache,
1, &epyc_l2_cache,
32 * KiB, &epyc_l3_cache,
64,
8,
1,
64,
1,
1,
true,
},
{
ICACHE,
1,
64 * KiB,
64,
4,
1,
256,
1,
1,
true,
},
{
UNIFIED_CACHE,
2,
512 * KiB,
64,
8,
1,
1024,
1,
},
{
UNIFIED_CACHE,
3,
8 * MiB,
64,
16,
1,
8192,
1,
true,
false,
true,
true,
},
}; };
static X86CPUDefinition builtin_x86_defs[] = { static X86CPUDefinition builtin_x86_defs[] = {
@ -3566,8 +3574,8 @@ static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp)
} }
/* Store Cache information from the X86CPUDefinition if available */ /* Store Cache information from the X86CPUDefinition if available */
env->cache_info = def->cache_info; /* legacy-cache defaults to 'off' if CPU model provides cache info */
cpu->legacy_cache = def->cache_info ? 0 : 1; cpu->legacy_cache = !def->cache_info;
if (tcg_enabled(env->uc)) { if (tcg_enabled(env->uc)) {
x86_cpu_apply_props(cpu, tcg_default_props); x86_cpu_apply_props(cpu, tcg_default_props);
@ -3692,21 +3700,11 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
if (!cpu->enable_l3_cache) { if (!cpu->enable_l3_cache) {
*ecx = 0; *ecx = 0;
} else { } else {
if (env->cache_info && !cpu->legacy_cache) { *ecx = cpuid2_cache_descriptor(env->cache_info_cpuid2.l3_cache);
*ecx = cpuid2_cache_descriptor(&env->cache_info->l3_cache);
} else {
*ecx = cpuid2_cache_descriptor(&legacy_l3_cache);
}
}
if (env->cache_info && !cpu->legacy_cache) {
*edx = (cpuid2_cache_descriptor(&env->cache_info->l1d_cache) << 16) |
(cpuid2_cache_descriptor(&env->cache_info->l1i_cache) << 8) |
(cpuid2_cache_descriptor(&env->cache_info->l2_cache));
} else {
*edx = (cpuid2_cache_descriptor(&legacy_l1d_cache) << 16) |
(cpuid2_cache_descriptor(&legacy_l1i_cache) << 8) |
(cpuid2_cache_descriptor(&legacy_l2_cache_cpuid2));
} }
*edx = (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1d_cache) << 16) |
(cpuid2_cache_descriptor(env->cache_info_cpuid2.l1i_cache) << 8) |
(cpuid2_cache_descriptor(env->cache_info_cpuid2.l2_cache));
break; break;
case 4: case 4:
/* cache info: needed for Core compatibility */ /* cache info: needed for Core compatibility */
@ -3719,35 +3717,27 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
} }
} else { } else {
*eax = 0; *eax = 0;
CPUCacheInfo *l1d, *l1i, *l2, *l3;
if (env->cache_info && !cpu->legacy_cache) {
l1d = &env->cache_info->l1d_cache;
l1i = &env->cache_info->l1i_cache;
l2 = &env->cache_info->l2_cache;
l3 = &env->cache_info->l3_cache;
} else {
l1d = &legacy_l1d_cache;
l1i = &legacy_l1i_cache;
l2 = &legacy_l2_cache;
l3 = &legacy_l3_cache;
}
switch (count) { switch (count) {
case 0: /* L1 dcache info */ case 0: /* L1 dcache info */
encode_cache_cpuid4(l1d, 1, cs->nr_cores, encode_cache_cpuid4(env->cache_info_cpuid4.l1d_cache,
1, cs->nr_cores,
eax, ebx, ecx, edx); eax, ebx, ecx, edx);
break; break;
case 1: /* L1 icache info */ case 1: /* L1 icache info */
encode_cache_cpuid4(l1i, 1, cs->nr_cores, encode_cache_cpuid4(env->cache_info_cpuid4.l1i_cache,
1, cs->nr_cores,
eax, ebx, ecx, edx); eax, ebx, ecx, edx);
break; break;
case 2: /* L2 cache info */ case 2: /* L2 cache info */
encode_cache_cpuid4(l2, cs->nr_threads, cs->nr_cores, encode_cache_cpuid4(env->cache_info_cpuid4.l2_cache,
cs->nr_threads, cs->nr_cores,
eax, ebx, ecx, edx); eax, ebx, ecx, edx);
break; break;
case 3: /* L3 cache info */ case 3: /* L3 cache info */
pkg_offset = apicid_pkg_offset(cs->nr_cores, cs->nr_threads); pkg_offset = apicid_pkg_offset(cs->nr_cores, cs->nr_threads);
if (cpu->enable_l3_cache) { if (cpu->enable_l3_cache) {
encode_cache_cpuid4(l3, (1 << pkg_offset), cs->nr_cores, encode_cache_cpuid4(env->cache_info_cpuid4.l3_cache,
(1 << pkg_offset), cs->nr_cores,
eax, ebx, ecx, edx); eax, ebx, ecx, edx);
break; break;
} }
@ -3951,13 +3941,8 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
(L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES); (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES);
*ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | \ *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | \
(L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES); (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES);
if (env->cache_info && !cpu->legacy_cache) { *ecx = encode_cache_cpuid80000005(env->cache_info_amd.l1d_cache);
*ecx = encode_cache_cpuid80000005(&env->cache_info->l1d_cache); *edx = encode_cache_cpuid80000005(env->cache_info_amd.l1i_cache);
*edx = encode_cache_cpuid80000005(&env->cache_info->l1i_cache);
} else {
*ecx = encode_cache_cpuid80000005(&legacy_l1d_cache_amd);
*edx = encode_cache_cpuid80000005(&legacy_l1i_cache_amd);
}
break; break;
case 0x80000006: case 0x80000006:
/* cache info (L2 cache) */ /* cache info (L2 cache) */
@ -3973,17 +3958,10 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
(L2_DTLB_4K_ENTRIES << 16) | \ (L2_DTLB_4K_ENTRIES << 16) | \
(AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | \ (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | \
(L2_ITLB_4K_ENTRIES); (L2_ITLB_4K_ENTRIES);
if (env->cache_info && !cpu->legacy_cache) { encode_cache_cpuid80000006(env->cache_info_amd.l2_cache,
encode_cache_cpuid80000006(&env->cache_info->l2_cache, cpu->enable_l3_cache ?
cpu->enable_l3_cache ? env->cache_info_amd.l3_cache : NULL,
&env->cache_info->l3_cache : NULL, ecx, edx);
ecx, edx);
} else {
encode_cache_cpuid80000006(&legacy_l2_cache_amd,
cpu->enable_l3_cache ?
&legacy_l3_cache : NULL,
ecx, edx);
}
break; break;
case 0x80000007: case 0x80000007:
*eax = 0; *eax = 0;
@ -4479,14 +4457,6 @@ static int x86_cpu_realizefn(struct uc_struct *uc, DeviceState *dev, Error **err
CPUX86State *env = &cpu->env; CPUX86State *env = &cpu->env;
Error *local_err = NULL; Error *local_err = NULL;
/* Unicorn: commented out
if (xcc->kvm_required && !kvm_enabled()) {
char *name = x86_cpu_class_get_model_name(xcc);
error_setg(&local_err, "CPU model '%s' requires KVM", name);
g_free(name);
goto out;
}*/
object_property_set_int(uc, OBJECT(cpu), CPU(cpu)->cpu_index, "apic-id", object_property_set_int(uc, OBJECT(cpu), CPU(cpu)->cpu_index, "apic-id",
&local_err); &local_err);
if (local_err) { if (local_err) {
@ -4558,6 +4528,37 @@ static int x86_cpu_realizefn(struct uc_struct *uc, DeviceState *dev, Error **err
} }
} }
/* Cache information initialization */
if (!cpu->legacy_cache) {
/* Unicorn: commented out
if (!xcc->cpu_def || !xcc->cpu_def->cache_info) {
char *name = x86_cpu_class_get_model_name(xcc);
error_setg(errp,
"CPU model '%s' doesn't support legacy-cache=off", name);
g_free(name);
return;
}
*/
env->cache_info_cpuid2 = env->cache_info_cpuid4 = env->cache_info_amd =
*xcc->cpu_def->cache_info;
} else {
/* Build legacy cache information */
env->cache_info_cpuid2.l1d_cache = &legacy_l1d_cache;
env->cache_info_cpuid2.l1i_cache = &legacy_l1i_cache;
env->cache_info_cpuid2.l2_cache = &legacy_l2_cache_cpuid2;
env->cache_info_cpuid2.l3_cache = &legacy_l3_cache;
env->cache_info_cpuid4.l1d_cache = &legacy_l1d_cache;
env->cache_info_cpuid4.l1i_cache = &legacy_l1i_cache;
env->cache_info_cpuid4.l2_cache = &legacy_l2_cache;
env->cache_info_cpuid4.l3_cache = &legacy_l3_cache;
env->cache_info_amd.l1d_cache = &legacy_l1d_cache_amd;
env->cache_info_amd.l1i_cache = &legacy_l1i_cache_amd;
env->cache_info_amd.l2_cache = &legacy_l2_cache_amd;
env->cache_info_amd.l3_cache = &legacy_l3_cache;
}
if (x86_cpu_filter_features(cpu) && cpu->enforce_cpuid) { if (x86_cpu_filter_features(cpu) && cpu->enforce_cpuid) {
error_setg(&local_err, error_setg(&local_err,
"TCG doesn't support requested features"); "TCG doesn't support requested features");

14
qemu/target/i386/cpu.h
View file

@ -1056,10 +1056,10 @@ typedef struct CPUCacheInfo {
} CPUCacheInfo; } CPUCacheInfo;
typedef struct CPUCaches { typedef struct CPUCaches {
CPUCacheInfo l1d_cache; CPUCacheInfo *l1d_cache;
CPUCacheInfo l1i_cache; CPUCacheInfo *l1i_cache;
CPUCacheInfo l2_cache; CPUCacheInfo *l2_cache;
CPUCacheInfo l3_cache; CPUCacheInfo *l3_cache;
} CPUCaches; } CPUCaches;
typedef struct CPUX86State { typedef struct CPUX86State {
@ -1237,7 +1237,11 @@ typedef struct CPUX86State {
/* Features that were explicitly enabled/disabled */ /* Features that were explicitly enabled/disabled */
FeatureWordArray user_features; FeatureWordArray user_features;
uint32_t cpuid_model[12]; uint32_t cpuid_model[12];
CPUCaches *cache_info; /* Cache information for CPUID. When legacy-cache=on, the cache data
* on each CPUID leaf will be different, because we keep compatibility
* with old QEMU versions.
*/
CPUCaches cache_info_cpuid2, cache_info_cpuid4, cache_info_amd;
/* MTRRs */ /* MTRRs */
uint64_t mtrr_fixed[11]; uint64_t mtrr_fixed[11];