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armv7m: add state for v7M CCR, CFSR, HFSR, DFSR, MMFAR, BFAR
Add the structure fields, VMState fields, reset code and macros for the v7M system control registers CCR, CFSR, HFSR, DFSR, MMFAR and BFAR. Backports commit 2c4da50d9477fb830d778bb5d6a11215aa359b44 from qemu
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@ -185,6 +185,12 @@ static void arm_cpu_reset(CPUState *s)
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}
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env->daif &= ~PSTATE_I;
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/* The reset value of this bit is IMPDEF, but ARM recommends
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* that it resets to 1, so QEMU always does that rather than making
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* it dependent on CPU model.
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*/
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env->v7m.ccr = R_V7M_CCR_STKALIGN_MASK;
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#if 0
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uint8_t *rom;
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rom = rom_ptr(0);
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@ -23,6 +23,7 @@
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#include "config.h"
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#include "kvm-consts.h"
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#include "hw/registerfields.h"
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#if defined(TARGET_AARCH64)
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/* AArch64 definitions */
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@ -414,6 +415,12 @@ typedef struct CPUARMState {
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uint32_t vecbase;
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uint32_t basepri;
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uint32_t control;
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uint32_t ccr; /* Configuration and Control */
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uint32_t cfsr; /* Configurable Fault Status */
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uint32_t hfsr; /* HardFault Status */
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uint32_t dfsr; /* Debug Fault Status Register */
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uint32_t mmfar; /* MemManage Fault Address */
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uint32_t bfar; /* BusFault Address */
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int exception;
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uint32_t secure; /* Is CPU in Secure state? (not guest visible) */
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} v7m;
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@ -1092,6 +1099,53 @@ enum arm_cpu_mode {
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#define ARM_IWMMXT_wCGR2 10
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#define ARM_IWMMXT_wCGR3 11
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/* V7M CCR bits */
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FIELD(V7M_CCR, NONBASETHRDENA, 0, 1)
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FIELD(V7M_CCR, USERSETMPEND, 1, 1)
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FIELD(V7M_CCR, UNALIGN_TRP, 3, 1)
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FIELD(V7M_CCR, DIV_0_TRP, 4, 1)
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FIELD(V7M_CCR, BFHFNMIGN, 8, 1)
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FIELD(V7M_CCR, STKALIGN, 9, 1)
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FIELD(V7M_CCR, DC, 16, 1)
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FIELD(V7M_CCR, IC, 17, 1)
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/* V7M CFSR bits for MMFSR */
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FIELD(V7M_CFSR, IACCVIOL, 0, 1)
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FIELD(V7M_CFSR, DACCVIOL, 1, 1)
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FIELD(V7M_CFSR, MUNSTKERR, 3, 1)
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FIELD(V7M_CFSR, MSTKERR, 4, 1)
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FIELD(V7M_CFSR, MLSPERR, 5, 1)
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FIELD(V7M_CFSR, MMARVALID, 7, 1)
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/* V7M CFSR bits for BFSR */
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FIELD(V7M_CFSR, IBUSERR, 8 + 0, 1)
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FIELD(V7M_CFSR, PRECISERR, 8 + 1, 1)
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FIELD(V7M_CFSR, IMPRECISERR, 8 + 2, 1)
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FIELD(V7M_CFSR, UNSTKERR, 8 + 3, 1)
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FIELD(V7M_CFSR, STKERR, 8 + 4, 1)
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FIELD(V7M_CFSR, LSPERR, 8 + 5, 1)
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FIELD(V7M_CFSR, BFARVALID, 8 + 7, 1)
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/* V7M CFSR bits for UFSR */
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FIELD(V7M_CFSR, UNDEFINSTR, 16 + 0, 1)
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FIELD(V7M_CFSR, INVSTATE, 16 + 1, 1)
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FIELD(V7M_CFSR, INVPC, 16 + 2, 1)
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FIELD(V7M_CFSR, NOCP, 16 + 3, 1)
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FIELD(V7M_CFSR, UNALIGNED, 16 + 8, 1)
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FIELD(V7M_CFSR, DIVBYZERO, 16 + 9, 1)
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/* V7M HFSR bits */
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FIELD(V7M_HFSR, VECTTBL, 1, 1)
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FIELD(V7M_HFSR, FORCED, 30, 1)
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FIELD(V7M_HFSR, DEBUGEVT, 31, 1)
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/* V7M DFSR bits */
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FIELD(V7M_DFSR, HALTED, 0, 1)
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FIELD(V7M_DFSR, BKPT, 1, 1)
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FIELD(V7M_DFSR, DWTTRAP, 2, 1)
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FIELD(V7M_DFSR, VCATCH, 3, 1)
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FIELD(V7M_DFSR, EXTERNAL, 4, 1)
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/* If adding a feature bit which corresponds to a Linux ELF
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* HWCAP bit, remember to update the feature-bit-to-hwcap
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* mapping in linux-user/elfload.c:get_elf_hwcap().
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