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target-m68k: Implement bitfield ops for memory

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Backports commit f2224f2c9a9ed63edaed77ae21ffb1e501d7f247 from qemu
This commit is contained in:
Richard Henderson 2018-03-01 19:01:11 -05:00 committed by Lioncash
parent 4f481b2c5a
commit 797e5d44e9
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GPG key ID: 4E3C3CC1031BA9C7
4 changed files with 337 additions and 2 deletions
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1
qemu/target-m68k/cpu.h
View file

@ -39,6 +39,7 @@
#define OS_DOUBLE 4
#define OS_EXTENDED 5
#define OS_PACKED 6
#define OS_UNSIZED 7
#define MAX_QREGS 32

8
qemu/target-m68k/helper.h
View file

@ -52,3 +52,11 @@ DEF_HELPER_2(flush_flags, void, env, i32)
DEF_HELPER_2(set_ccr, void, env, i32)
DEF_HELPER_FLAGS_1(get_ccr, TCG_CALL_NO_WG_SE, i32, env)
DEF_HELPER_2(raise_exception, void, env, i32)
DEF_HELPER_FLAGS_4(bfexts_mem, TCG_CALL_NO_WG, i32, env, i32, s32, i32)
DEF_HELPER_FLAGS_4(bfextu_mem, TCG_CALL_NO_WG, i64, env, i32, s32, i32)
DEF_HELPER_FLAGS_5(bfins_mem, TCG_CALL_NO_WG, i32, env, i32, i32, s32, i32)
DEF_HELPER_FLAGS_4(bfchg_mem, TCG_CALL_NO_WG, i32, env, i32, s32, i32)
DEF_HELPER_FLAGS_4(bfclr_mem, TCG_CALL_NO_WG, i32, env, i32, s32, i32)
DEF_HELPER_FLAGS_4(bfset_mem, TCG_CALL_NO_WG, i32, env, i32, s32, i32)

185
qemu/target-m68k/op_helper.c
View file

@ -461,3 +461,188 @@ void HELPER(cas2l)(CPUM68KState *env, uint32_t regs, uint32_t a1, uint32_t a2)
env->dregs[Dc2] = l2;
}
struct bf_data {
uint32_t addr;
uint32_t bofs;
uint32_t blen;
uint32_t len;
};
static struct bf_data bf_prep(uint32_t addr, int32_t ofs, uint32_t len)
{
int bofs, blen;
struct bf_data result;
/* Bound length; map 0 to 32. */
len = ((len - 1) & 31) + 1;
/* Note that ofs is signed. */
addr += ofs / 8;
bofs = ofs % 8;
if (bofs < 0) {
bofs += 8;
addr -= 1;
}
/* Compute the number of bytes required (minus one) to
satisfy the bitfield. */
blen = (bofs + len - 1) / 8;
/* Canonicalize the bit offset for data loaded into a 64-bit big-endian
word. For the cases where BLEN is not a power of 2, adjust ADDR so
that we can use the next power of two sized load without crossing a
page boundary, unless the field itself crosses the boundary. */
switch (blen) {
case 0:
bofs += 56;
break;
case 1:
bofs += 48;
break;
case 2:
if (addr & 1) {
bofs += 8;
addr -= 1;
}
/* fallthru */
case 3:
bofs += 32;
break;
case 4:
if (addr & 3) {
bofs += 8 * (addr & 3);
addr &= -4;
}
break;
default:
g_assert_not_reached();
}
result.addr = addr;
result.bofs = bofs;
result.blen = blen;
result.len = len;
return result;
}
static uint64_t bf_load(CPUM68KState *env, uint32_t addr, int blen,
uintptr_t ra)
{
switch (blen) {
case 0:
return cpu_ldub_data_ra(env, addr, ra);
case 1:
return cpu_lduw_data_ra(env, addr, ra);
case 2:
case 3:
return cpu_ldl_data_ra(env, addr, ra);
case 4:
return cpu_ldq_data_ra(env, addr, ra);
default:
g_assert_not_reached();
}
}
static void bf_store(CPUM68KState *env, uint32_t addr, int blen,
uint64_t data, uintptr_t ra)
{
switch (blen) {
case 0:
cpu_stb_data_ra(env, addr, data, ra);
break;
case 1:
cpu_stw_data_ra(env, addr, data, ra);
break;
case 2:
case 3:
cpu_stl_data_ra(env, addr, data, ra);
break;
case 4:
cpu_stq_data_ra(env, addr, data, ra);
break;
default:
g_assert_not_reached();
}
}
uint32_t HELPER(bfexts_mem)(CPUM68KState *env, uint32_t addr,
int32_t ofs, uint32_t len)
{
uintptr_t ra = GETPC();
struct bf_data d = bf_prep(addr, ofs, len);
uint64_t data = bf_load(env, d.addr, d.blen, ra);
return (int64_t)(data << d.bofs) >> (64 - d.len);
}
uint64_t HELPER(bfextu_mem)(CPUM68KState *env, uint32_t addr,
int32_t ofs, uint32_t len)
{
uintptr_t ra = GETPC();
struct bf_data d = bf_prep(addr, ofs, len);
uint64_t data = bf_load(env, d.addr, d.blen, ra);
/* Put CC_N at the top of the high word; put the zero-extended value
at the bottom of the low word. */
data <<= d.bofs;
data >>= 64 - d.len;
data |= data << (64 - d.len);
return data;
}
uint32_t HELPER(bfins_mem)(CPUM68KState *env, uint32_t addr, uint32_t val,
int32_t ofs, uint32_t len)
{
uintptr_t ra = GETPC();
struct bf_data d = bf_prep(addr, ofs, len);
uint64_t data = bf_load(env, d.addr, d.blen, ra);
uint64_t mask = -1ull << (64 - d.len) >> d.bofs;
data = (data & ~mask) | (((uint64_t)val << (64 - d.len)) >> d.bofs);
bf_store(env, d.addr, d.blen, data, ra);
/* The field at the top of the word is also CC_N for CC_OP_LOGIC. */
return val << (32 - d.len);
}
uint32_t HELPER(bfchg_mem)(CPUM68KState *env, uint32_t addr,
int32_t ofs, uint32_t len)
{
uintptr_t ra = GETPC();
struct bf_data d = bf_prep(addr, ofs, len);
uint64_t data = bf_load(env, d.addr, d.blen, ra);
uint64_t mask = -1ull << (64 - d.len) >> d.bofs;
bf_store(env, d.addr, d.blen, data ^ mask, ra);
return ((data & mask) << d.bofs) >> 32;
}
uint32_t HELPER(bfclr_mem)(CPUM68KState *env, uint32_t addr,
int32_t ofs, uint32_t len)
{
uintptr_t ra = GETPC();
struct bf_data d = bf_prep(addr, ofs, len);
uint64_t data = bf_load(env, d.addr, d.blen, ra);
uint64_t mask = -1ull << (64 - d.len) >> d.bofs;
bf_store(env, d.addr, d.blen, data & ~mask, ra);
return ((data & mask) << d.bofs) >> 32;
}
uint32_t HELPER(bfset_mem)(CPUM68KState *env, uint32_t addr,
int32_t ofs, uint32_t len)
{
uintptr_t ra = GETPC();
struct bf_data d = bf_prep(addr, ofs, len);
uint64_t data = bf_load(env, d.addr, d.blen, ra);
uint64_t mask = -1ull << (64 - d.len) >> d.bofs;
bf_store(env, d.addr, d.blen, data | mask, ra);
return ((data & mask) << d.bofs) >> 32;
}

145
qemu/target-m68k/translate.c
View file

@ -711,10 +711,17 @@ static TCGv gen_lea_mode(CPUM68KState *env, DisasContext *s,
case 0: /* Data register direct. */
case 1: /* Address register direct. */
return tcg_ctx->NULL_QREG;
case 3: /* Indirect postincrement */
if (opsize == OS_UNSIZED) {
return tcg_ctx->NULL_QREG;
}
/* fallthru */
case 2: /* Indirect register */
case 3: /* Indirect postincrement. */
return get_areg(s, reg0);
case 4: /* Indirect predecrememnt. */
if (opsize == OS_UNSIZED) {
return tcg_ctx->NULL_QREG;
}
reg = get_areg(s, reg0);
tmp = tcg_temp_new(tcg_ctx);
tcg_gen_subi_i32(tcg_ctx, tmp, reg, opsize_bytes(opsize));
@ -3709,6 +3716,50 @@ DISAS_INSN(bfext_reg)
set_cc_op(s, CC_OP_LOGIC);
}
DISAS_INSN(bfext_mem)
{
TCGContext *tcg_ctx = s->uc->tcg_ctx;
int ext = read_im16(env, s);
int is_sign = insn & 0x200;
TCGv dest = DREG(ext, 12);
TCGv addr, len, ofs;
addr = gen_lea(env, s, insn, OS_UNSIZED);
if (IS_NULL_QREG(addr)) {
gen_addr_fault(s);
return;
}
if (ext & 0x20) {
len = DREG(ext, 0);
} else {
len = tcg_const_i32(tcg_ctx, extract32(ext, 0, 5));
}
if (ext & 0x800) {
ofs = DREG(ext, 6);
} else {
ofs = tcg_const_i32(tcg_ctx, extract32(ext, 6, 5));
}
if (is_sign) {
gen_helper_bfexts_mem(tcg_ctx, dest, tcg_ctx->cpu_env, addr, ofs, len);
tcg_gen_mov_i32(tcg_ctx, tcg_ctx->QREG_CC_N, dest);
} else {
TCGv_i64 tmp = tcg_temp_new_i64(tcg_ctx);
gen_helper_bfextu_mem(tcg_ctx, tmp, tcg_ctx->cpu_env, addr, ofs, len);
tcg_gen_extr_i64_i32(tcg_ctx, dest, tcg_ctx->QREG_CC_N, tmp);
tcg_temp_free_i64(tcg_ctx, tmp);
}
set_cc_op(s, CC_OP_LOGIC);
if (!(ext & 0x20)) {
tcg_temp_free(tcg_ctx, len);
}
if (!(ext & 0x800)) {
tcg_temp_free(tcg_ctx, ofs);
}
}
DISAS_INSN(bfop_reg)
{
TCGContext *tcg_ctx = s->uc->tcg_ctx;
@ -3775,6 +3826,55 @@ DISAS_INSN(bfop_reg)
tcg_temp_free(tcg_ctx, mask);
}
DISAS_INSN(bfop_mem)
{
TCGContext *tcg_ctx = s->uc->tcg_ctx;
int ext = read_im16(env, s);
TCGv addr, len, ofs;
addr = gen_lea(env, s, insn, OS_UNSIZED);
if (IS_NULL_QREG(addr)) {
gen_addr_fault(s);
return;
}
if (ext & 0x20) {
len = DREG(ext, 0);
} else {
len = tcg_const_i32(tcg_ctx, extract32(ext, 0, 5));
}
if (ext & 0x800) {
ofs = DREG(ext, 6);
} else {
ofs = tcg_const_i32(tcg_ctx, extract32(ext, 6, 5));
}
switch (insn & 0x0f00) {
case 0x0a00: /* bfchg */
gen_helper_bfchg_mem(tcg_ctx, tcg_ctx->QREG_CC_N, tcg_ctx->cpu_env, addr, ofs, len);
break;
case 0x0c00: /* bfclr */
gen_helper_bfclr_mem(tcg_ctx, tcg_ctx->QREG_CC_N, tcg_ctx->cpu_env, addr, ofs, len);
break;
case 0x0e00: /* bfset */
gen_helper_bfset_mem(tcg_ctx, tcg_ctx->QREG_CC_N, tcg_ctx->cpu_env, addr, ofs, len);
break;
case 0x0800: /* bftst */
gen_helper_bfexts_mem(tcg_ctx, tcg_ctx->QREG_CC_N, tcg_ctx->cpu_env, addr, ofs, len);
break;
default:
g_assert_not_reached();
}
set_cc_op(s, CC_OP_LOGIC);
if (!(ext & 0x20)) {
tcg_temp_free(tcg_ctx, len);
}
if (!(ext & 0x800)) {
tcg_temp_free(tcg_ctx, ofs);
}
}
DISAS_INSN(bfins_reg)
{
TCGContext *tcg_ctx = s->uc->tcg_ctx;
@ -3850,6 +3950,41 @@ DISAS_INSN(bfins_reg)
tcg_temp_free(tcg_ctx, tmp);
}
DISAS_INSN(bfins_mem)
{
TCGContext *tcg_ctx = s->uc->tcg_ctx;
int ext = read_im16(env, s);
TCGv src = DREG(ext, 12);
TCGv addr, len, ofs;
addr = gen_lea(env, s, insn, OS_UNSIZED);
if (IS_NULL_QREG(addr)) {
gen_addr_fault(s);
return;
}
if (ext & 0x20) {
len = DREG(ext, 0);
} else {
len = tcg_const_i32(tcg_ctx, extract32(ext, 0, 5));
}
if (ext & 0x800) {
ofs = DREG(ext, 6);
} else {
ofs = tcg_const_i32(tcg_ctx, extract32(ext, 6, 5));
}
gen_helper_bfins_mem(tcg_ctx, tcg_ctx->QREG_CC_N, tcg_ctx->cpu_env, addr, src, ofs, len);
set_cc_op(s, CC_OP_LOGIC);
if (!(ext & 0x20)) {
tcg_temp_free(tcg_ctx, len);
}
if (!(ext & 0x800)) {
tcg_temp_free(tcg_ctx, ofs);
}
}
DISAS_INSN(ff1)
{
TCGContext *tcg_ctx = s->uc->tcg_ctx;
@ -4971,11 +5106,17 @@ void register_m68k_insns (CPUM68KState *env)
INSN(rotate8_reg, e030, f0f0, M68000);
INSN(rotate16_reg, e070, f0f0, M68000);
INSN(rotate_mem, e4c0, fcc0, M68000);
INSN(bfext_reg, e9c0, fdf8, BITFIELD); /* bfextu & bfexts */
INSN(bfext_mem, e9c0, fdc0, BITFIELD); /* bfextu & bfexts */
INSN(bfext_reg, e9c0, fdf8, BITFIELD);
INSN(bfins_mem, efc0, ffc0, BITFIELD);
INSN(bfins_reg, efc0, fff8, BITFIELD);
INSN(bfop_mem, eac0, ffc0, BITFIELD); /* bfchg */
INSN(bfop_reg, eac0, fff8, BITFIELD); /* bfchg */
INSN(bfop_mem, ecc0, ffc0, BITFIELD); /* bfclr */
INSN(bfop_reg, ecc0, fff8, BITFIELD); /* bfclr */
INSN(bfop_mem, eec0, ffc0, BITFIELD); /* bfset */
INSN(bfop_reg, eec0, fff8, BITFIELD); /* bfset */
INSN(bfop_mem, e8c0, ffc0, BITFIELD); /* bftst */
INSN(bfop_reg, e8c0, fff8, BITFIELD); /* bftst */
INSN(undef_fpu, f000, f000, CF_ISA_A);
INSN(fpu, f200, ffc0, CF_FPU);