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target-arm: Simplify insn_crosses_page()
Recent changes have left insn_crosses_page() more complicated than it needed to be: * it's only called from thumb_tr_translate_insn() so we know for certain that we're looking at a Thumb insn * the caller's check for dc->pc >= dc->next_page_start - 3 means that dc->pc can't possibly be 4 aligned, so there's no need to check that (the check was partly there to ensure that we didn't treat an ARM insn as Thumb, I think) * we now have thumb_insn_is_16bit() which lets us do a precise check of the length of the next insn, rather than opencoding an inaccurate check Simplify it down to just loading the first half of the insn and calling thumb_insn_is_16bit() on it. Backports commit 5b8d7289e9e92a0d7bcecb93cd189e245fef10cd from qemu
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@ -12083,29 +12083,14 @@ static bool insn_crosses_page(CPUARMState *env, DisasContext *s)
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{
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/* Return true if the insn at dc->pc might cross a page boundary.
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* (False positives are OK, false negatives are not.)
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* We know this is a Thumb insn, and our caller ensures we are
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* only called if dc->pc is less than 4 bytes from the page
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* boundary, so we cross the page if the first 16 bits indicate
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* that this is a 32 bit insn.
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*/
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uint16_t insn;
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uint16_t insn = arm_lduw_code(env, s->pc, s->sctlr_b);
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if ((s->pc & 3) == 0) {
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/* At a 4-aligned address we can't be crossing a page */
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return false;
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}
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/* This must be a Thumb insn */
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insn = arm_lduw_code(env, s->pc, s->sctlr_b);
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if ((insn >> 11) >= 0x1d) {
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/* Top five bits 0b11101 / 0b11110 / 0b11111 : this is the
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* First half of a 32-bit Thumb insn. Thumb-1 cores might
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* end up actually treating this as two 16-bit insns (see the
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* code at the start of disas_thumb2_insn()) but we don't bother
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* to check for that as it is unlikely, and false positives here
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* are harmless.
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*/
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return true;
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}
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/* Definitely a 16-bit insn, can't be crossing a page. */
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return false;
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return !thumb_insn_is_16bit(s, insn);
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}
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static int arm_tr_init_disas_context(DisasContextBase *dcbase,
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