tcg: Add tcg_op_supported

Backports commit be0f34b5840312bbe9627c2b9f68a25f32903dae from qemu

qemu/aarch64.h

@@ -3204,6 +3204,7 @@
 #define tcg_op_insert_after tcg_op_insert_after_aarch64
 #define tcg_op_insert_before tcg_op_insert_before_aarch64
 #define tcg_op_remove tcg_op_remove_aarch64
+#define tcg_op_supported tcg_op_supported_aarch64
 #define tcg_opt_gen_mov tcg_opt_gen_mov_aarch64
 #define tcg_opt_gen_movi tcg_opt_gen_movi_aarch64
 #define tcg_optimize tcg_optimize_aarch64

qemu/aarch64eb.h

@@ -3204,6 +3204,7 @@
 #define tcg_op_insert_after tcg_op_insert_after_aarch64eb
 #define tcg_op_insert_before tcg_op_insert_before_aarch64eb
 #define tcg_op_remove tcg_op_remove_aarch64eb
+#define tcg_op_supported tcg_op_supported_aarch64eb
 #define tcg_opt_gen_mov tcg_opt_gen_mov_aarch64eb
 #define tcg_opt_gen_movi tcg_opt_gen_movi_aarch64eb
 #define tcg_optimize tcg_optimize_aarch64eb

qemu/arm.h

@@ -3204,6 +3204,7 @@
 #define tcg_op_insert_after tcg_op_insert_after_arm
 #define tcg_op_insert_before tcg_op_insert_before_arm
 #define tcg_op_remove tcg_op_remove_arm
+#define tcg_op_supported tcg_op_supported_arm
 #define tcg_opt_gen_mov tcg_opt_gen_mov_arm
 #define tcg_opt_gen_movi tcg_opt_gen_movi_arm
 #define tcg_optimize tcg_optimize_arm

qemu/armeb.h

@@ -3204,6 +3204,7 @@
 #define tcg_op_insert_after tcg_op_insert_after_armeb
 #define tcg_op_insert_before tcg_op_insert_before_armeb
 #define tcg_op_remove tcg_op_remove_armeb
+#define tcg_op_supported tcg_op_supported_armeb
 #define tcg_opt_gen_mov tcg_opt_gen_mov_armeb
 #define tcg_opt_gen_movi tcg_opt_gen_movi_armeb
 #define tcg_optimize tcg_optimize_armeb

qemu/header_gen.py

@@ -2935,7 +2935,6 @@ symbols = (
     'target_el_table',
     'target_parse_constraint',
     'target_words_bigendian',
-    #'tb_add_jump',
     'tb_alloc',
     'tb_alloc_page',
     'tb_check_watchpoint',
@@ -3211,6 +3210,7 @@ symbols = (
     'tcg_op_insert_after',
     'tcg_op_insert_before',
     'tcg_op_remove',
+    'tcg_op_supported',
     'tcg_opt_gen_mov',
     'tcg_opt_gen_movi',
     'tcg_optimize',

qemu/m68k.h

@@ -3204,6 +3204,7 @@
 #define tcg_op_insert_after tcg_op_insert_after_m68k
 #define tcg_op_insert_before tcg_op_insert_before_m68k
 #define tcg_op_remove tcg_op_remove_m68k
+#define tcg_op_supported tcg_op_supported_m68k
 #define tcg_opt_gen_mov tcg_opt_gen_mov_m68k
 #define tcg_opt_gen_movi tcg_opt_gen_movi_m68k
 #define tcg_optimize tcg_optimize_m68k

qemu/mips.h

@@ -3204,6 +3204,7 @@
 #define tcg_op_insert_after tcg_op_insert_after_mips
 #define tcg_op_insert_before tcg_op_insert_before_mips
 #define tcg_op_remove tcg_op_remove_mips
+#define tcg_op_supported tcg_op_supported_mips
 #define tcg_opt_gen_mov tcg_opt_gen_mov_mips
 #define tcg_opt_gen_movi tcg_opt_gen_movi_mips
 #define tcg_optimize tcg_optimize_mips

qemu/mips64.h

@@ -3204,6 +3204,7 @@
 #define tcg_op_insert_after tcg_op_insert_after_mips64
 #define tcg_op_insert_before tcg_op_insert_before_mips64
 #define tcg_op_remove tcg_op_remove_mips64
+#define tcg_op_supported tcg_op_supported_mips64
 #define tcg_opt_gen_mov tcg_opt_gen_mov_mips64
 #define tcg_opt_gen_movi tcg_opt_gen_movi_mips64
 #define tcg_optimize tcg_optimize_mips64

qemu/mips64el.h

@@ -3204,6 +3204,7 @@
 #define tcg_op_insert_after tcg_op_insert_after_mips64el
 #define tcg_op_insert_before tcg_op_insert_before_mips64el
 #define tcg_op_remove tcg_op_remove_mips64el
+#define tcg_op_supported tcg_op_supported_mips64el
 #define tcg_opt_gen_mov tcg_opt_gen_mov_mips64el
 #define tcg_opt_gen_movi tcg_opt_gen_movi_mips64el
 #define tcg_optimize tcg_optimize_mips64el

qemu/mipsel.h

@@ -3204,6 +3204,7 @@
 #define tcg_op_insert_after tcg_op_insert_after_mipsel
 #define tcg_op_insert_before tcg_op_insert_before_mipsel
 #define tcg_op_remove tcg_op_remove_mipsel
+#define tcg_op_supported tcg_op_supported_mipsel
 #define tcg_opt_gen_mov tcg_opt_gen_mov_mipsel
 #define tcg_opt_gen_movi tcg_opt_gen_movi_mipsel
 #define tcg_optimize tcg_optimize_mipsel

qemu/powerpc.h

@@ -3204,6 +3204,7 @@
 #define tcg_op_insert_after tcg_op_insert_after_powerpc
 #define tcg_op_insert_before tcg_op_insert_before_powerpc
 #define tcg_op_remove tcg_op_remove_powerpc
+#define tcg_op_supported tcg_op_supported_powerpc
 #define tcg_opt_gen_mov tcg_opt_gen_mov_powerpc
 #define tcg_opt_gen_movi tcg_opt_gen_movi_powerpc
 #define tcg_optimize tcg_optimize_powerpc

qemu/sparc.h

@@ -3204,6 +3204,7 @@
 #define tcg_op_insert_after tcg_op_insert_after_sparc
 #define tcg_op_insert_before tcg_op_insert_before_sparc
 #define tcg_op_remove tcg_op_remove_sparc
+#define tcg_op_supported tcg_op_supported_sparc
 #define tcg_opt_gen_mov tcg_opt_gen_mov_sparc
 #define tcg_opt_gen_movi tcg_opt_gen_movi_sparc
 #define tcg_optimize tcg_optimize_sparc

qemu/sparc64.h

@@ -3204,6 +3204,7 @@
 #define tcg_op_insert_after tcg_op_insert_after_sparc64
 #define tcg_op_insert_before tcg_op_insert_before_sparc64
 #define tcg_op_remove tcg_op_remove_sparc64
+#define tcg_op_supported tcg_op_supported_sparc64
 #define tcg_opt_gen_mov tcg_opt_gen_mov_sparc64
 #define tcg_opt_gen_movi tcg_opt_gen_movi_sparc64
 #define tcg_optimize tcg_optimize_sparc64

qemu/tcg/tcg.c

@@ -740,6 +740,229 @@ int tcg_check_temp_count(TCGContext *s)
 }
 #endif
 
+/* Return true if OP may appear in the opcode stream.
+   Test the runtime variable that controls each opcode.  */
+bool tcg_op_supported(TCGOpcode op)
+{
+    switch (op) {
+    case INDEX_op_discard:
+    case INDEX_op_set_label:
+    case INDEX_op_call:
+    case INDEX_op_br:
+    case INDEX_op_mb:
+    case INDEX_op_insn_start:
+    case INDEX_op_exit_tb:
+    case INDEX_op_goto_tb:
+    case INDEX_op_qemu_ld_i32:
+    case INDEX_op_qemu_st_i32:
+    case INDEX_op_qemu_ld_i64:
+    case INDEX_op_qemu_st_i64:
+        return true;
+
+    case INDEX_op_goto_ptr:
+        return TCG_TARGET_HAS_goto_ptr;
+
+    case INDEX_op_mov_i32:
+    case INDEX_op_movi_i32:
+    case INDEX_op_setcond_i32:
+    case INDEX_op_brcond_i32:
+    case INDEX_op_ld8u_i32:
+    case INDEX_op_ld8s_i32:
+    case INDEX_op_ld16u_i32:
+    case INDEX_op_ld16s_i32:
+    case INDEX_op_ld_i32:
+    case INDEX_op_st8_i32:
+    case INDEX_op_st16_i32:
+    case INDEX_op_st_i32:
+    case INDEX_op_add_i32:
+    case INDEX_op_sub_i32:
+    case INDEX_op_mul_i32:
+    case INDEX_op_and_i32:
+    case INDEX_op_or_i32:
+    case INDEX_op_xor_i32:
+    case INDEX_op_shl_i32:
+    case INDEX_op_shr_i32:
+    case INDEX_op_sar_i32:
+        return true;
+
+    case INDEX_op_movcond_i32:
+        return TCG_TARGET_HAS_movcond_i32;
+    case INDEX_op_div_i32:
+    case INDEX_op_divu_i32:
+        return TCG_TARGET_HAS_div_i32;
+    case INDEX_op_rem_i32:
+    case INDEX_op_remu_i32:
+        return TCG_TARGET_HAS_rem_i32;
+    case INDEX_op_div2_i32:
+    case INDEX_op_divu2_i32:
+        return TCG_TARGET_HAS_div2_i32;
+    case INDEX_op_rotl_i32:
+    case INDEX_op_rotr_i32:
+        return TCG_TARGET_HAS_rot_i32;
+    case INDEX_op_deposit_i32:
+        return TCG_TARGET_HAS_deposit_i32;
+    case INDEX_op_extract_i32:
+        return TCG_TARGET_HAS_extract_i32;
+    case INDEX_op_sextract_i32:
+        return TCG_TARGET_HAS_sextract_i32;
+    case INDEX_op_add2_i32:
+        return TCG_TARGET_HAS_add2_i32;
+    case INDEX_op_sub2_i32:
+        return TCG_TARGET_HAS_sub2_i32;
+    case INDEX_op_mulu2_i32:
+        return TCG_TARGET_HAS_mulu2_i32;
+    case INDEX_op_muls2_i32:
+        return TCG_TARGET_HAS_muls2_i32;
+    case INDEX_op_muluh_i32:
+        return TCG_TARGET_HAS_muluh_i32;
+    case INDEX_op_mulsh_i32:
+        return TCG_TARGET_HAS_mulsh_i32;
+    case INDEX_op_ext8s_i32:
+        return TCG_TARGET_HAS_ext8s_i32;
+    case INDEX_op_ext16s_i32:
+        return TCG_TARGET_HAS_ext16s_i32;
+    case INDEX_op_ext8u_i32:
+        return TCG_TARGET_HAS_ext8u_i32;
+    case INDEX_op_ext16u_i32:
+        return TCG_TARGET_HAS_ext16u_i32;
+    case INDEX_op_bswap16_i32:
+        return TCG_TARGET_HAS_bswap16_i32;
+    case INDEX_op_bswap32_i32:
+        return TCG_TARGET_HAS_bswap32_i32;
+    case INDEX_op_not_i32:
+        return TCG_TARGET_HAS_not_i32;
+    case INDEX_op_neg_i32:
+        return TCG_TARGET_HAS_neg_i32;
+    case INDEX_op_andc_i32:
+        return TCG_TARGET_HAS_andc_i32;
+    case INDEX_op_orc_i32:
+        return TCG_TARGET_HAS_orc_i32;
+    case INDEX_op_eqv_i32:
+        return TCG_TARGET_HAS_eqv_i32;
+    case INDEX_op_nand_i32:
+        return TCG_TARGET_HAS_nand_i32;
+    case INDEX_op_nor_i32:
+        return TCG_TARGET_HAS_nor_i32;
+    case INDEX_op_clz_i32:
+        return TCG_TARGET_HAS_clz_i32;
+    case INDEX_op_ctz_i32:
+        return TCG_TARGET_HAS_ctz_i32;
+    case INDEX_op_ctpop_i32:
+        return TCG_TARGET_HAS_ctpop_i32;
+
+    case INDEX_op_brcond2_i32:
+    case INDEX_op_setcond2_i32:
+        return TCG_TARGET_REG_BITS == 32;
+
+    case INDEX_op_mov_i64:
+    case INDEX_op_movi_i64:
+    case INDEX_op_setcond_i64:
+    case INDEX_op_brcond_i64:
+    case INDEX_op_ld8u_i64:
+    case INDEX_op_ld8s_i64:
+    case INDEX_op_ld16u_i64:
+    case INDEX_op_ld16s_i64:
+    case INDEX_op_ld32u_i64:
+    case INDEX_op_ld32s_i64:
+    case INDEX_op_ld_i64:
+    case INDEX_op_st8_i64:
+    case INDEX_op_st16_i64:
+    case INDEX_op_st32_i64:
+    case INDEX_op_st_i64:
+    case INDEX_op_add_i64:
+    case INDEX_op_sub_i64:
+    case INDEX_op_mul_i64:
+    case INDEX_op_and_i64:
+    case INDEX_op_or_i64:
+    case INDEX_op_xor_i64:
+    case INDEX_op_shl_i64:
+    case INDEX_op_shr_i64:
+    case INDEX_op_sar_i64:
+    case INDEX_op_ext_i32_i64:
+    case INDEX_op_extu_i32_i64:
+        return TCG_TARGET_REG_BITS == 64;
+
+    case INDEX_op_movcond_i64:
+        return TCG_TARGET_HAS_movcond_i64;
+    case INDEX_op_div_i64:
+    case INDEX_op_divu_i64:
+        return TCG_TARGET_HAS_div_i64;
+    case INDEX_op_rem_i64:
+    case INDEX_op_remu_i64:
+        return TCG_TARGET_HAS_rem_i64;
+    case INDEX_op_div2_i64:
+    case INDEX_op_divu2_i64:
+        return TCG_TARGET_HAS_div2_i64;
+    case INDEX_op_rotl_i64:
+    case INDEX_op_rotr_i64:
+        return TCG_TARGET_HAS_rot_i64;
+    case INDEX_op_deposit_i64:
+        return TCG_TARGET_HAS_deposit_i64;
+    case INDEX_op_extract_i64:
+        return TCG_TARGET_HAS_extract_i64;
+    case INDEX_op_sextract_i64:
+        return TCG_TARGET_HAS_sextract_i64;
+    case INDEX_op_extrl_i64_i32:
+        return TCG_TARGET_HAS_extrl_i64_i32;
+    case INDEX_op_extrh_i64_i32:
+        return TCG_TARGET_HAS_extrh_i64_i32;
+    case INDEX_op_ext8s_i64:
+        return TCG_TARGET_HAS_ext8s_i64;
+    case INDEX_op_ext16s_i64:
+        return TCG_TARGET_HAS_ext16s_i64;
+    case INDEX_op_ext32s_i64:
+        return TCG_TARGET_HAS_ext32s_i64;
+    case INDEX_op_ext8u_i64:
+        return TCG_TARGET_HAS_ext8u_i64;
+    case INDEX_op_ext16u_i64:
+        return TCG_TARGET_HAS_ext16u_i64;
+    case INDEX_op_ext32u_i64:
+        return TCG_TARGET_HAS_ext32u_i64;
+    case INDEX_op_bswap16_i64:
+        return TCG_TARGET_HAS_bswap16_i64;
+    case INDEX_op_bswap32_i64:
+        return TCG_TARGET_HAS_bswap32_i64;
+    case INDEX_op_bswap64_i64:
+        return TCG_TARGET_HAS_bswap64_i64;
+    case INDEX_op_not_i64:
+        return TCG_TARGET_HAS_not_i64;
+    case INDEX_op_neg_i64:
+        return TCG_TARGET_HAS_neg_i64;
+    case INDEX_op_andc_i64:
+        return TCG_TARGET_HAS_andc_i64;
+    case INDEX_op_orc_i64:
+        return TCG_TARGET_HAS_orc_i64;
+    case INDEX_op_eqv_i64:
+        return TCG_TARGET_HAS_eqv_i64;
+    case INDEX_op_nand_i64:
+        return TCG_TARGET_HAS_nand_i64;
+    case INDEX_op_nor_i64:
+        return TCG_TARGET_HAS_nor_i64;
+    case INDEX_op_clz_i64:
+        return TCG_TARGET_HAS_clz_i64;
+    case INDEX_op_ctz_i64:
+        return TCG_TARGET_HAS_ctz_i64;
+    case INDEX_op_ctpop_i64:
+        return TCG_TARGET_HAS_ctpop_i64;
+    case INDEX_op_add2_i64:
+        return TCG_TARGET_HAS_add2_i64;
+    case INDEX_op_sub2_i64:
+        return TCG_TARGET_HAS_sub2_i64;
+    case INDEX_op_mulu2_i64:
+        return TCG_TARGET_HAS_mulu2_i64;
+    case INDEX_op_muls2_i64:
+        return TCG_TARGET_HAS_muls2_i64;
+    case INDEX_op_muluh_i64:
+        return TCG_TARGET_HAS_muluh_i64;
+    case INDEX_op_mulsh_i64:
+        return TCG_TARGET_HAS_mulsh_i64;
+
+    case NB_OPS:
+        break;
+    }
+    g_assert_not_reached();
+}
+
 /* Note: we convert the 64 bit args to 32 bit and do some alignment
    and endian swap. Maybe it would be better to do the alignment
    and endian swap in tcg_reg_alloc_call(). */
@@ -2734,9 +2957,7 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb)
             break;
         default:
             /* Sanity check that we've not introduced any unhandled opcodes. */
-            if (def->flags & TCG_OPF_NOT_PRESENT) {
+            tcg_debug_assert(tcg_op_supported(opc));
-                tcg_abort();
-            }
             /* Note: in order to speed up the code, it would be much
                faster to have specialized register allocator functions for
                some common argument patterns */

qemu/tcg/tcg.h

@@ -1051,6 +1051,8 @@ do {\
 #define tcg_temp_free_ptr(s, T) tcg_temp_free_i64(s, TCGV_PTR_TO_NAT(T))
 #endif
 
+bool tcg_op_supported(TCGOpcode op);
+
 void tcg_gen_callN(TCGContext *s, void *func,
                    TCGArg ret, int nargs, TCGArg *args);
 

qemu/x86_64.h

@@ -3204,6 +3204,7 @@
 #define tcg_op_insert_after tcg_op_insert_after_x86_64
 #define tcg_op_insert_before tcg_op_insert_before_x86_64
 #define tcg_op_remove tcg_op_remove_x86_64
+#define tcg_op_supported tcg_op_supported_x86_64
 #define tcg_opt_gen_mov tcg_opt_gen_mov_x86_64
 #define tcg_opt_gen_movi tcg_opt_gen_movi_x86_64
 #define tcg_optimize tcg_optimize_x86_64