target/arm: Convert integer-to-float insns to decodetree

Convert the VCVT integer-to-float instructions to decodetree.

Backports commit 8fc9d8918cde342c71923e361b9f2193e36ed18b from qemu

qemu/target/arm/translate-vfp.inc.c

@@ -2407,3 +2407,63 @@ static bool trans_VCVT_dp(DisasContext *s, arg_VCVT_dp *a)
     tcg_temp_free_i64(tcg_ctx, vm);
     return true;
 }
+
+static bool trans_VCVT_int_sp(DisasContext *s, arg_VCVT_int_sp *a)
+{
+    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    TCGv_i32 vm;
+    TCGv_ptr fpst;
+
+    if (!vfp_access_check(s)) {
+        return true;
+    }
+
+    vm = tcg_temp_new_i32(tcg_ctx);
+    neon_load_reg32(s, vm, a->vm);
+    fpst = get_fpstatus_ptr(s, false);
+    if (a->s) {
+        /* i32 -> f32 */
+        gen_helper_vfp_sitos(tcg_ctx, vm, vm, fpst);
+    } else {
+        /* u32 -> f32 */
+        gen_helper_vfp_uitos(tcg_ctx, vm, vm, fpst);
+    }
+    neon_store_reg32(s, vm, a->vd);
+    tcg_temp_free_i32(tcg_ctx, vm);
+    tcg_temp_free_ptr(tcg_ctx, fpst);
+    return true;
+}
+
+static bool trans_VCVT_int_dp(DisasContext *s, arg_VCVT_int_dp *a)
+{
+    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    TCGv_i32 vm;
+    TCGv_i64 vd;
+    TCGv_ptr fpst;
+
+    /* UNDEF accesses to D16-D31 if they don't exist. */
+    if (!dc_isar_feature(aa32_fp_d32, s) && (a->vd & 0x10)) {
+        return false;
+    }
+
+    if (!vfp_access_check(s)) {
+        return true;
+    }
+
+    vm = tcg_temp_new_i32(tcg_ctx);
+    vd = tcg_temp_new_i64(tcg_ctx);
+    neon_load_reg32(s, vm, a->vm);
+    fpst = get_fpstatus_ptr(s, false);
+    if (a->s) {
+        /* i32 -> f64 */
+        gen_helper_vfp_sitod(tcg_ctx, vd, vm, fpst);
+    } else {
+        /* u32 -> f64 */
+        gen_helper_vfp_uitod(tcg_ctx, vd, vm, fpst);
+    }
+    neon_store_reg64(s, vd, a->vd);
+    tcg_temp_free_i32(tcg_ctx, vm);
+    tcg_temp_free_i64(tcg_ctx, vd);
+    tcg_temp_free_ptr(tcg_ctx, fpst);
+    return true;
+}

qemu/target/arm/translate.c

@@ -3145,7 +3145,7 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)
                 return 1;
             case 15:
                 switch (rn) {
-                case 0 ... 15:
+                case 0 ... 17:
                     /* Already handled by decodetree */
                     return 1;
                 default:
@@ -3158,10 +3158,6 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)
             if (op == 15) {
                 /* rn is opcode, encoded as per VFP_SREG_N. */
                 switch (rn) {
-                case 0x10: /* vcvt.fxx.u32 */
-                case 0x11: /* vcvt.fxx.s32 */
-                    rm_is_dp = false;
-                    break;
                 case 0x18: /* vcvtr.u32.fxx */
                 case 0x19: /* vcvtz.u32.fxx */
                 case 0x1a: /* vcvtr.s32.fxx */
@@ -3276,12 +3272,6 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)
                 switch (op) {
                 case 15: /* extension space */
                     switch (rn) {
-                    case 16: /* fuito */
-                        gen_vfp_uito(s, dp, 0);
-                        break;
-                    case 17: /* fsito */
-                        gen_vfp_sito(s, dp, 0);
-                        break;
                     case 19: /* vjcvt */
                         gen_helper_vjcvt(tcg_ctx, s->F0s, s->F0d, tcg_ctx->cpu_env);
                         break;

qemu/target/arm/vfp.decode

@@ -214,3 +214,9 @@ VCVT_sp      ---- 1110 1.11 0111 .... 1010 11.0 .... \
              vd=%vd_dp vm=%vm_sp
 VCVT_dp      ---- 1110 1.11 0111 .... 1011 11.0 .... \
              vd=%vd_sp vm=%vm_dp
+
+# VCVT from integer to floating point: Vm always single; Vd depends on size
+VCVT_int_sp  ---- 1110 1.11 1000 .... 1010 s:1 1.0 .... \
+             vd=%vd_sp vm=%vm_sp
+VCVT_int_dp  ---- 1110 1.11 1000 .... 1011 s:1 1.0 .... \
+             vd=%vd_dp vm=%vm_sp