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target-i386: emulate LOCK'ed OP instructions using atomic helpers

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Backports commit a7cee522f3529c2fc85379237b391ea98823271e from qemu
This commit is contained in:
Emilio G. Cota 2018-02-27 22:49:18 -05:00 committed by Lioncash
parent a386368f82
commit 7c7b0fe746
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 58 additions and 20 deletions
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78
qemu/target-i386/translate.c
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@ -1454,55 +1454,93 @@ static void gen_op(DisasContext *s, int op, TCGMemOp ot, int d)
if (d != OR_TMP0) { if (d != OR_TMP0) {
gen_op_mov_v_reg(tcg_ctx, ot, cpu_T0, d); gen_op_mov_v_reg(tcg_ctx, ot, cpu_T0, d);
} else { } else if (!(s->prefix & PREFIX_LOCK)) {
gen_op_ld_v(s, ot, cpu_T0, cpu_A0); gen_op_ld_v(s, ot, cpu_T0, cpu_A0);
} }
switch(op) { switch(op) {
case OP_ADCL: case OP_ADCL:
gen_compute_eflags_c(s, cpu_tmp4); if (s->prefix & PREFIX_LOCK) {
tcg_gen_add_tl(tcg_ctx, cpu_T0, cpu_T0, cpu_T1); tcg_gen_add_tl(tcg_ctx, cpu_T0, cpu_tmp4, cpu_T1);
tcg_gen_add_tl(tcg_ctx, cpu_T0, cpu_T0, cpu_tmp4); tcg_gen_atomic_add_fetch_tl(tcg_ctx, cpu_T0, cpu_A0, cpu_T0,
gen_op_st_rm_T0_A0(s, ot, d); s->mem_index, ot | MO_LE);
} else {
tcg_gen_add_tl(tcg_ctx, cpu_T0, cpu_T0, cpu_T1);
tcg_gen_add_tl(tcg_ctx, cpu_T0, cpu_T0, cpu_tmp4);
gen_op_st_rm_T0_A0(s, ot, d);
}
gen_op_update3_cc(tcg_ctx, cpu_tmp4); gen_op_update3_cc(tcg_ctx, cpu_tmp4);
set_cc_op(s, CC_OP_ADCB + ot); set_cc_op(s, CC_OP_ADCB + ot);
break; break;
case OP_SBBL: case OP_SBBL:
gen_compute_eflags_c(s, cpu_tmp4); if (s->prefix & PREFIX_LOCK) {
tcg_gen_sub_tl(tcg_ctx, cpu_T0, cpu_T0, cpu_T1); tcg_gen_add_tl(tcg_ctx, cpu_T0, cpu_T1, cpu_tmp4);
tcg_gen_sub_tl(tcg_ctx, cpu_T0, cpu_T0, cpu_tmp4); tcg_gen_neg_tl(tcg_ctx, cpu_T0, cpu_T0);
gen_op_st_rm_T0_A0(s, ot, d); tcg_gen_atomic_add_fetch_tl(tcg_ctx, cpu_T0, cpu_A0, cpu_T0,
s->mem_index, ot | MO_LE);
} else {
tcg_gen_sub_tl(tcg_ctx, cpu_T0, cpu_T0, cpu_T1);
tcg_gen_sub_tl(tcg_ctx, cpu_T0, cpu_T0, cpu_tmp4);
gen_op_st_rm_T0_A0(s, ot, d);
}
gen_op_update3_cc(tcg_ctx, cpu_tmp4); gen_op_update3_cc(tcg_ctx, cpu_tmp4);
set_cc_op(s, CC_OP_SBBB + ot); set_cc_op(s, CC_OP_SBBB + ot);
break; break;
case OP_ADDL: case OP_ADDL:
tcg_gen_add_tl(tcg_ctx, cpu_T0, cpu_T0, cpu_T1); if (s->prefix & PREFIX_LOCK) {
gen_op_st_rm_T0_A0(s, ot, d); tcg_gen_atomic_add_fetch_tl(tcg_ctx, cpu_T0, cpu_A0, cpu_T1,
s->mem_index, ot | MO_LE);
} else {
tcg_gen_add_tl(tcg_ctx, cpu_T0, cpu_T0, cpu_T1);
gen_op_st_rm_T0_A0(s, ot, d);
}
gen_op_update2_cc(tcg_ctx); gen_op_update2_cc(tcg_ctx);
set_cc_op(s, CC_OP_ADDB + ot); set_cc_op(s, CC_OP_ADDB + ot);
break; break;
case OP_SUBL: case OP_SUBL:
tcg_gen_mov_tl(tcg_ctx, cpu_cc_srcT, cpu_T0); if (s->prefix & PREFIX_LOCK) {
tcg_gen_sub_tl(tcg_ctx, cpu_T0, cpu_T0, cpu_T1); tcg_gen_neg_tl(tcg_ctx, cpu_T0, cpu_T1);
gen_op_st_rm_T0_A0(s, ot, d); tcg_gen_atomic_fetch_add_tl(tcg_ctx, cpu_cc_srcT, cpu_A0, cpu_T0,
s->mem_index, ot | MO_LE);
tcg_gen_sub_tl(tcg_ctx, cpu_T0, cpu_cc_srcT, cpu_T1);
} else {
tcg_gen_mov_tl(tcg_ctx, cpu_cc_srcT, cpu_T0);
tcg_gen_sub_tl(tcg_ctx, cpu_T0, cpu_T0, cpu_T1);
gen_op_st_rm_T0_A0(s, ot, d);
}
gen_op_update2_cc(tcg_ctx); gen_op_update2_cc(tcg_ctx);
set_cc_op(s, CC_OP_SUBB + ot); set_cc_op(s, CC_OP_SUBB + ot);
break; break;
default: default:
case OP_ANDL: case OP_ANDL:
tcg_gen_and_tl(tcg_ctx, cpu_T0, cpu_T0, cpu_T1); if (s->prefix & PREFIX_LOCK) {
gen_op_st_rm_T0_A0(s, ot, d); tcg_gen_atomic_and_fetch_tl(tcg_ctx, cpu_T0, cpu_A0, cpu_T1,
s->mem_index, ot | MO_LE);
} else {
tcg_gen_and_tl(tcg_ctx, cpu_T0, cpu_T0, cpu_T1);
gen_op_st_rm_T0_A0(s, ot, d);
}
gen_op_update1_cc(tcg_ctx); gen_op_update1_cc(tcg_ctx);
set_cc_op(s, CC_OP_LOGICB + ot); set_cc_op(s, CC_OP_LOGICB + ot);
break; break;
case OP_ORL: case OP_ORL:
tcg_gen_or_tl(tcg_ctx, cpu_T0, cpu_T0, cpu_T1); if (s->prefix & PREFIX_LOCK) {
gen_op_st_rm_T0_A0(s, ot, d); tcg_gen_atomic_or_fetch_tl(tcg_ctx, cpu_T0, cpu_A0, cpu_T1,
s->mem_index, ot | MO_LE);
} else {
tcg_gen_or_tl(tcg_ctx, cpu_T0, cpu_T0, cpu_T1);
gen_op_st_rm_T0_A0(s, ot, d);
}
gen_op_update1_cc(tcg_ctx); gen_op_update1_cc(tcg_ctx);
set_cc_op(s, CC_OP_LOGICB + ot); set_cc_op(s, CC_OP_LOGICB + ot);
break; break;
case OP_XORL: case OP_XORL:
tcg_gen_xor_tl(tcg_ctx, cpu_T0, cpu_T0, cpu_T1); if (s->prefix & PREFIX_LOCK) {
gen_op_st_rm_T0_A0(s, ot, d); tcg_gen_atomic_xor_fetch_tl(tcg_ctx, cpu_T0, cpu_A0, cpu_T1,
s->mem_index, ot | MO_LE);
} else {
tcg_gen_xor_tl(tcg_ctx, cpu_T0, cpu_T0, cpu_T1);
gen_op_st_rm_T0_A0(s, ot, d);
}
gen_op_update1_cc(tcg_ctx); gen_op_update1_cc(tcg_ctx);
set_cc_op(s, CC_OP_LOGICB + ot); set_cc_op(s, CC_OP_LOGICB + ot);
break; break;