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armv7m: Improve "-d mmu" tracing for PMSAv7 MPU

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Improve the "-d mmu" tracing for the PMSAv7 MPU translation
process as an aid in debugging guest MPU configurations:
* fix a missing newline for a guest-error log
* report the region number with guest-error or unimp
logs of bad region register values
* add a log message for the overall result of the lookup
* print "0x" prefix for hex values

Backports commit c9f9f1246d630960bce45881e9c0d27b55be71e2 from qemu
This commit is contained in:
Michael Davidsaver 2018-03-02 19:16:52 -05:00 committed by Lioncash
parent bfe99e9a0b
commit 7c845dabe8
No known key found for this signature in database
GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 27 additions and 12 deletions
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37
qemu/target/arm/helper.c
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@ -7319,16 +7319,18 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
} }
if (!rsize) { if (!rsize) {
qemu_log_mask(LOG_GUEST_ERROR, "DRSR.Rsize field can not be 0"); qemu_log_mask(LOG_GUEST_ERROR,
"DRSR[%d]: Rsize field cannot be 0\n", n);
continue; continue;
} }
rsize++; rsize++;
rmask = (1ull << rsize) - 1; rmask = (1ull << rsize) - 1;
if (base & rmask) { if (base & rmask) {
qemu_log_mask(LOG_GUEST_ERROR, "DRBAR %" PRIx32 " misaligned " qemu_log_mask(LOG_GUEST_ERROR,
"to DRSR region size, mask = %" PRIx32, "DRBAR[%d]: 0x%" PRIx32 " misaligned "
base, rmask); "to DRSR region size, mask = 0x%" PRIx32 "\n",
n, base, rmask);
continue; continue;
} }
@ -7365,9 +7367,10 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
} }
} }
if (rsize < TARGET_PAGE_BITS) { if (rsize < TARGET_PAGE_BITS) {
qemu_log_mask(LOG_UNIMP, "No support for MPU (sub)region" qemu_log_mask(LOG_UNIMP,
"DRSR[%d]: No support for MPU (sub)region "
"alignment of %" PRIu32 " bits. Minimum is %d\n", "alignment of %" PRIu32 " bits. Minimum is %d\n",
rsize, TARGET_PAGE_BITS); n, rsize, TARGET_PAGE_BITS);
continue; continue;
} }
if (srdis) { if (srdis) {
@ -7401,8 +7404,8 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
break; break;
default: default:
qemu_log_mask(LOG_GUEST_ERROR, qemu_log_mask(LOG_GUEST_ERROR,
"Bad value for AP bits in DRACR %" "DRACR[%d]: Bad value for AP bits: 0x%"
PRIx32 "\n", ap); PRIx32 "\n", n, ap);
} }
} else { /* Priv. mode AP bits decoding */ } else { /* Priv. mode AP bits decoding */
switch (ap) { switch (ap) {
@ -7419,8 +7422,8 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
break; break;
default: default:
qemu_log_mask(LOG_GUEST_ERROR, qemu_log_mask(LOG_GUEST_ERROR,
"Bad value for AP bits in DRACR %" "DRACR[%d]: Bad value for AP bits: 0x%"
PRIx32 "\n", ap); PRIx32 "\n", n, ap);
} }
} }
@ -7598,9 +7601,21 @@ static bool get_phys_addr(CPUARMState *env, target_ulong address,
*/ */
if (arm_feature(env, ARM_FEATURE_PMSA) && if (arm_feature(env, ARM_FEATURE_PMSA) &&
arm_feature(env, ARM_FEATURE_V7)) { arm_feature(env, ARM_FEATURE_V7)) {
bool ret;
*page_size = TARGET_PAGE_SIZE; *page_size = TARGET_PAGE_SIZE;
return get_phys_addr_pmsav7(env, address, access_type, mmu_idx, ret = get_phys_addr_pmsav7(env, address, access_type, mmu_idx,
phys_ptr, prot, fsr); phys_ptr, prot, fsr);
qemu_log_mask(CPU_LOG_MMU, "PMSAv7 MPU lookup for %s at 0x%08" PRIx32
" mmu_idx %u -> %s (prot %c%c%c)\n",
access_type == 1 ? "reading" :
(access_type == 2 ? "writing" : "execute"),
(uint32_t)address, mmu_idx,
ret ? "Miss" : "Hit",
*prot & PAGE_READ ? 'r' : '-',
*prot & PAGE_WRITE ? 'w' : '-',
*prot & PAGE_EXEC ? 'x' : '-');
return ret;
} }
if (regime_translation_disabled(env, mmu_idx)) { if (regime_translation_disabled(env, mmu_idx)) {