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target-arm/helper.c: define MPUIR register

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Define the MPUIR register for MPU supporting ARMv6 and onwards.
Currently we only support unified MPU.

The size of the unified MPU is defined via the number of "dregions".
So just a single config is added to specify this size. (When split MPU
is implemented we will add an extra iregions config).

Backports commit 3281af8114c6b8ead02f08b58e3c36895c1ea047 from qemu
This commit is contained in:
Peter Crosthwaite 2018-02-13 15:35:04 -05:00 committed by Lioncash
parent 07ead14756
commit 7d933a6ba9
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GPG key ID: 4E3C3CC1031BA9C7
3 changed files with 20 additions and 0 deletions
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2
qemu/target-arm/cpu-qom.h
View file

@ -104,6 +104,8 @@ typedef struct ARMCPU {
/* CPU has memory protection unit */
bool has_mpu;
/* PMSAv7 MPU number of supported regions */
uint32_t pmsav7_dregion;
/* PSCI conduit used to invoke PSCI methods
* 0 - disabled, 1 - smc, 2 - hvc

10
qemu/target-arm/cpu.c
View file

@ -489,6 +489,16 @@ static int arm_cpu_realizefn(struct uc_struct *uc, DeviceState *dev, Error **err
unset_feature(env, ARM_FEATURE_MPU);
}
if (arm_feature(env, ARM_FEATURE_MPU) &&
arm_feature(env, ARM_FEATURE_V7)) {
uint32_t nr = cpu->pmsav7_dregion;
if (nr > 0xff) {
error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32 "\n", nr);
return -1;
}
}
if (arm_feature(env, ARM_FEATURE_EL3)) {
set_feature(env, ARM_FEATURE_VBAR);
}

8
qemu/target-arm/helper.c
View file

@ -2970,6 +2970,11 @@ void register_cp_regs_for_features(ARMCPU *cpu)
"TLBTR", 15,0,0, 0,0,3, 0,
ARM_CP_CONST, PL1_R, 0, NULL, 0,
};
/* MPUIR is specific to PMSA V6+ */
ARMCPRegInfo id_mpuir_reginfo = {
"MPUIR", 15,0,0, 0,0,4, 0,ARM_CP_CONST,
PL1_R, 0, NULL, cpu->pmsav7_dregion << 8
};
ARMCPRegInfo crn0_wi_reginfo = {
"CRN0_WI", 15,0,CP_ANY, 0,CP_ANY,CP_ANY, 0,
ARM_CP_NOP | ARM_CP_OVERRIDE, PL1_W,
@ -2991,6 +2996,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
r->access = PL1_RW;
}
id_tlbtr_reginfo.access = PL1_RW;
id_tlbtr_reginfo.access = PL1_RW;
}
if (arm_feature(env, ARM_FEATURE_V8)) {
define_arm_cp_regs(cpu, id_v8_midr_cp_reginfo);
@ -3000,6 +3006,8 @@ void register_cp_regs_for_features(ARMCPU *cpu)
define_arm_cp_regs(cpu, id_cp_reginfo);
if (!arm_feature(env, ARM_FEATURE_MPU)) {
define_one_arm_cp_reg(cpu, &id_tlbtr_reginfo);
} else if (arm_feature(env, ARM_FEATURE_V7)) {
define_one_arm_cp_reg(cpu, &id_mpuir_reginfo);
}
}