target/arm: Restrict the values of DCZID.BS under TCG

We can simplify our DC_ZVA if we recognize that the largest BS
that we actually use in system mode is 64. Let us just assert
that it fits within TARGET_PAGE_SIZE.

For DC_GVA and STZGM, we want to be able to write whole bytes
of tag memory, so assert that BS is >= 2 * TAG_GRANULE, or 32.

Backports commit a4157b80242bf1c8aa0ee77aae7458ba79012d5d from qemu
This commit is contained in:
Richard Henderson 2021-02-25 15:12:19 -05:00 committed by Lioncash
parent e15aa7c5a7
commit 7de60598d5

View file

@ -1023,6 +1023,30 @@ static int arm_cpu_realizefn(struct uc_struct *uc, DeviceState *dev, Error **err
} }
#endif #endif
if (tcg_enabled(uc)) {
int dcz_blocklen = 4 << cpu->dcz_blocksize;
/*
* We only support DCZ blocklen that fits on one page.
*
* Architectually this is always true. However TARGET_PAGE_SIZE
* is variable and, for compatibility with -machine virt-2.7,
* is only 1KiB, as an artifact of legacy ARMv5 subpage support.
* But even then, while the largest architectural DCZ blocklen
* is 2KiB, no cpu actually uses such a large blocklen.
*/
assert(dcz_blocklen <= TARGET_PAGE_SIZE);
/*
* We only support DCZ blocksize >= 2*TAG_GRANULE, which is to say
* both nibbles of each byte storing tag data may be written at once.
* Since TAG_GRANULE is 16, this means that blocklen must be >= 32.
*/
if (cpu_isar_feature(aa64_mte, cpu)) {
assert(dcz_blocklen >= 2 * TAG_GRANULE);
}
}
qemu_init_vcpu(cs); qemu_init_vcpu(cs);
cpu_reset(cs); cpu_reset(cs);