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https://github.com/yuzu-emu/unicorn.git
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target/arm: Move cpu_get_tb_cpu_state out of line
Backports commit a9e013112f03bf1644a549a769be599a3ceb6155 from qemu
This commit is contained in:
Richard Henderson
Lioncash
parent
404fa33c4b
commit
7dfbe4e104
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@ -2577,71 +2577,6 @@ static inline bool bswap_code(bool sctlr_b)
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#endif
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}
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/* Return the exception level to which FP-disabled exceptions should
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* be taken, or 0 if FP is enabled.
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*/
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static inline int fp_exception_el(CPUARMState *env)
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{
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int fpen;
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int cur_el = arm_current_el(env);
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/* CPACR and the CPTR registers don't exist before v6, so FP is
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* always accessible
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*/
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if (!arm_feature(env, ARM_FEATURE_V6)) {
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return 0;
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}
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/* The CPACR controls traps to EL1, or PL1 if we're 32 bit:
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* 0, 2 : trap EL0 and EL1/PL1 accesses
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* 1 : trap only EL0 accesses
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* 3 : trap no accesses
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*/
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fpen = extract32(env->cp15.cpacr_el1, 20, 2);
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switch (fpen) {
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case 0:
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case 2:
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if (cur_el == 0 || cur_el == 1) {
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/* Trap to PL1, which might be EL1 or EL3 */
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if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) {
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return 3;
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}
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return 1;
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}
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if (cur_el == 3 && !is_a64(env)) {
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/* Secure PL1 running at EL3 */
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return 3;
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}
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break;
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case 1:
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if (cur_el == 0) {
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return 1;
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}
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break;
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case 3:
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break;
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}
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/* For the CPTR registers we don't need to guard with an ARM_FEATURE
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* check because zero bits in the registers mean "don't trap".
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*/
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/* CPTR_EL2 : present in v7VE or v8 */
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if (cur_el <= 2 && extract32(env->cp15.cptr_el[2], 10, 1)
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&& !arm_is_secure_below_el3(env)) {
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/* Trap FP ops at EL2, NS-EL1 or NS-EL0 to EL2 */
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return 2;
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}
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/* CPTR_EL3 : present in v8 */
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if (extract32(env->cp15.cptr_el[3], 10, 1)) {
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/* Trap all FP ops to EL3 */
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return 3;
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}
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return 0;
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}
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static inline bool arm_sctlr_b(CPUARMState *env)
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{
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return
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@ -2724,94 +2659,8 @@ static inline uint32_t arm_regime_tbi1(CPUARMState *env, ARMMMUIdx mmu_idx)
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}
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#endif
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static inline void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
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target_ulong *cs_base, uint32_t *flags)
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{
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ARMMMUIdx mmu_idx = core_to_arm_mmu_idx(env, cpu_mmu_index(env, false));
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if (is_a64(env)) {
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*pc = env->pc;
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*flags = ARM_TBFLAG_AARCH64_STATE_MASK;
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/* Get control bits for tagged addresses */
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*flags |= (arm_regime_tbi0(env, mmu_idx) << ARM_TBFLAG_TBI0_SHIFT);
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*flags |= (arm_regime_tbi1(env, mmu_idx) << ARM_TBFLAG_TBI1_SHIFT);
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} else {
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*pc = env->regs[15];
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*flags = (env->thumb << ARM_TBFLAG_THUMB_SHIFT)
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| (env->vfp.vec_len << ARM_TBFLAG_VECLEN_SHIFT)
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| (env->vfp.vec_stride << ARM_TBFLAG_VECSTRIDE_SHIFT)
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| (env->condexec_bits << ARM_TBFLAG_CONDEXEC_SHIFT)
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| (arm_sctlr_b(env) << ARM_TBFLAG_SCTLR_B_SHIFT);
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if (!(access_secure_reg(env))) {
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*flags |= ARM_TBFLAG_NS_MASK;
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}
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if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)
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|| arm_el_is_aa64(env, 1)) {
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*flags |= ARM_TBFLAG_VFPEN_MASK;
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}
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*flags |= (extract32(env->cp15.c15_cpar, 0, 2)
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<< ARM_TBFLAG_XSCALE_CPAR_SHIFT);
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}
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*flags |= (arm_to_core_mmu_idx(mmu_idx) << ARM_TBFLAG_MMUIDX_SHIFT);
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/* The SS_ACTIVE and PSTATE_SS bits correspond to the state machine
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* states defined in the ARM ARM for software singlestep:
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* SS_ACTIVE PSTATE.SS State
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* 0 x Inactive (the TB flag for SS is always 0)
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* 1 0 Active-pending
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* 1 1 Active-not-pending
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*/
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if (arm_singlestep_active(env)) {
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*flags |= ARM_TBFLAG_SS_ACTIVE_MASK;
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if (is_a64(env)) {
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if (env->pstate & PSTATE_SS) {
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*flags |= ARM_TBFLAG_PSTATE_SS_MASK;
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}
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} else {
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if (env->uncached_cpsr & PSTATE_SS) {
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*flags |= ARM_TBFLAG_PSTATE_SS_MASK;
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}
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}
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}
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if (arm_cpu_data_is_big_endian(env)) {
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*flags |= ARM_TBFLAG_BE_DATA_MASK;
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}
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*flags |= fp_exception_el(env) << ARM_TBFLAG_FPEXC_EL_SHIFT;
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if (arm_v7m_is_handler_mode(env)) {
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*flags |= ARM_TBFLAG_HANDLER_MASK;
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}
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*cs_base = 0;
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}
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/**
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* aa32_vfp_dreg:
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* Return a pointer to the Dn register within env in 32-bit mode.
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*/
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static inline uint64_t *aa32_vfp_dreg(CPUARMState *env, unsigned regno)
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{
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return &env->vfp.regs[regno];
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}
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/**
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* aa32_vfp_qreg:
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* Return a pointer to the Qn register within env in 32-bit mode.
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*/
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static inline uint64_t *aa32_vfp_qreg(CPUARMState *env, unsigned regno)
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{
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return &env->vfp.regs[2 * regno];
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}
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/**
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* aa64_vfp_qreg:
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* Return a pointer to the Qn register within env in 64-bit mode.
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*/
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static inline uint64_t *aa64_vfp_qreg(CPUARMState *env, unsigned regno)
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{
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return &env->vfp.regs[2 * regno];
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}
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void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
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target_ulong *cs_base, uint32_t *flags);
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enum {
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QEMU_PSCI_CONDUIT_DISABLED = 0,
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@ -2860,4 +2709,31 @@ static inline void *arm_get_el_change_hook_opaque(ARMCPU *cpu)
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return cpu->el_change_hook_opaque;
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}
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/**
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* aa32_vfp_dreg:
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* Return a pointer to the Dn register within env in 32-bit mode.
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*/
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static inline uint64_t *aa32_vfp_dreg(CPUARMState *env, unsigned regno)
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{
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return &env->vfp.regs[regno];
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}
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/**
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* aa32_vfp_qreg:
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* Return a pointer to the Qn register within env in 32-bit mode.
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*/
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static inline uint64_t *aa32_vfp_qreg(CPUARMState *env, unsigned regno)
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{
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return &env->vfp.regs[2 * regno];
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}
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/**
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* aa64_vfp_qreg:
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* Return a pointer to the Qn register within env in 64-bit mode.
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*/
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static inline uint64_t *aa64_vfp_qreg(CPUARMState *env, unsigned regno)
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{
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return &env->vfp.regs[2 * regno];
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}
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#endif
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@ -10827,3 +10827,129 @@ uint32_t HELPER(crc32c)(uint32_t acc, uint32_t val, uint32_t bytes)
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/* Linux crc32c converts the output to one's complement. */
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return crc32c(acc, buf, bytes) ^ 0xffffffff;
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}
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/* Return the exception level to which FP-disabled exceptions should
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* be taken, or 0 if FP is enabled.
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*/
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static inline int fp_exception_el(CPUARMState *env)
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{
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int fpen;
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int cur_el = arm_current_el(env);
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/* CPACR and the CPTR registers don't exist before v6, so FP is
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* always accessible
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*/
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if (!arm_feature(env, ARM_FEATURE_V6)) {
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return 0;
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}
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/* The CPACR controls traps to EL1, or PL1 if we're 32 bit:
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* 0, 2 : trap EL0 and EL1/PL1 accesses
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* 1 : trap only EL0 accesses
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* 3 : trap no accesses
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*/
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fpen = extract32(env->cp15.cpacr_el1, 20, 2);
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switch (fpen) {
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case 0:
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case 2:
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if (cur_el == 0 || cur_el == 1) {
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/* Trap to PL1, which might be EL1 or EL3 */
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if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) {
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return 3;
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}
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return 1;
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}
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if (cur_el == 3 && !is_a64(env)) {
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/* Secure PL1 running at EL3 */
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return 3;
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}
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break;
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case 1:
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if (cur_el == 0) {
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return 1;
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}
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break;
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case 3:
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break;
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}
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/* For the CPTR registers we don't need to guard with an ARM_FEATURE
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* check because zero bits in the registers mean "don't trap".
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*/
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/* CPTR_EL2 : present in v7VE or v8 */
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if (cur_el <= 2 && extract32(env->cp15.cptr_el[2], 10, 1)
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&& !arm_is_secure_below_el3(env)) {
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/* Trap FP ops at EL2, NS-EL1 or NS-EL0 to EL2 */
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return 2;
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}
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/* CPTR_EL3 : present in v8 */
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if (extract32(env->cp15.cptr_el[3], 10, 1)) {
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/* Trap all FP ops to EL3 */
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return 3;
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}
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return 0;
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}
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void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
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target_ulong *cs_base, uint32_t *flags)
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{
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ARMMMUIdx mmu_idx = core_to_arm_mmu_idx(env, cpu_mmu_index(env, false));
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if (is_a64(env)) {
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*pc = env->pc;
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*flags = ARM_TBFLAG_AARCH64_STATE_MASK;
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/* Get control bits for tagged addresses */
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*flags |= (arm_regime_tbi0(env, mmu_idx) << ARM_TBFLAG_TBI0_SHIFT);
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*flags |= (arm_regime_tbi1(env, mmu_idx) << ARM_TBFLAG_TBI1_SHIFT);
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} else {
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*pc = env->regs[15];
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*flags = (env->thumb << ARM_TBFLAG_THUMB_SHIFT)
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| (env->vfp.vec_len << ARM_TBFLAG_VECLEN_SHIFT)
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| (env->vfp.vec_stride << ARM_TBFLAG_VECSTRIDE_SHIFT)
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| (env->condexec_bits << ARM_TBFLAG_CONDEXEC_SHIFT)
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| (arm_sctlr_b(env) << ARM_TBFLAG_SCTLR_B_SHIFT);
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if (!(access_secure_reg(env))) {
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*flags |= ARM_TBFLAG_NS_MASK;
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}
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if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)
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|| arm_el_is_aa64(env, 1)) {
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*flags |= ARM_TBFLAG_VFPEN_MASK;
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}
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*flags |= (extract32(env->cp15.c15_cpar, 0, 2)
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<< ARM_TBFLAG_XSCALE_CPAR_SHIFT);
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}
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*flags |= (arm_to_core_mmu_idx(mmu_idx) << ARM_TBFLAG_MMUIDX_SHIFT);
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/* The SS_ACTIVE and PSTATE_SS bits correspond to the state machine
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* states defined in the ARM ARM for software singlestep:
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* SS_ACTIVE PSTATE.SS State
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* 0 x Inactive (the TB flag for SS is always 0)
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* 1 0 Active-pending
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* 1 1 Active-not-pending
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*/
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if (arm_singlestep_active(env)) {
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*flags |= ARM_TBFLAG_SS_ACTIVE_MASK;
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if (is_a64(env)) {
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if (env->pstate & PSTATE_SS) {
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*flags |= ARM_TBFLAG_PSTATE_SS_MASK;
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}
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} else {
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if (env->uncached_cpsr & PSTATE_SS) {
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*flags |= ARM_TBFLAG_PSTATE_SS_MASK;
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}
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}
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}
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if (arm_cpu_data_is_big_endian(env)) {
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*flags |= ARM_TBFLAG_BE_DATA_MASK;
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}
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*flags |= fp_exception_el(env) << ARM_TBFLAG_FPEXC_EL_SHIFT;
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if (arm_v7m_is_handler_mode(env)) {
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*flags |= ARM_TBFLAG_HANDLER_MASK;
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}
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*cs_base = 0;
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}
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