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https://github.com/yuzu-emu/unicorn.git
synced 2024-12-23 14:35:34 +00:00
target/mips: Add availability control via bit NMS
A set of nanoMIPS instructions is not available if Config5 bit NMS is set. Backports commit fb32f8c8560be7ca4e323cee1b839701126401d1 from qemu
This commit is contained in:
Dimitrije Nikolic
Lioncash
parent
38f2640a34
commit
7e0342c9f6
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@ -1963,6 +1963,17 @@ static inline void check_cp0_mt(DisasContext *ctx)
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}
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#endif
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/*
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* This code generates a "reserved instruction" exception if the
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* Config5 NMS bit is set.
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*/
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static inline void check_nms(DisasContext *ctx)
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{
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if (unlikely(ctx->CP0_Config5 & (1 << CP0C5_NMS))) {
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generate_exception_end(ctx, EXCP_RI);
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}
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}
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/* Define small wrappers for gen_load_fpr* so that we have a uniform
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calling interface for 32 and 64-bit FPRs. No sense in changing
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@ -17118,17 +17129,21 @@ static void gen_pool32a0_nanomips_insn(CPUMIPSState *env, DisasContext *ctx)
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case NM_P_TRAP:
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switch (extract32(ctx->opcode, 10, 1)) {
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case NM_TEQ:
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check_nms(ctx);
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gen_trap(ctx, OPC_TEQ, rs, rt, -1);
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break;
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case NM_TNE:
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check_nms(ctx);
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gen_trap(ctx, OPC_TNE, rs, rt, -1);
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break;
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}
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break;
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case NM_RDHWR:
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check_nms(ctx);
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gen_rdhwr(ctx, rt, rs, extract32(ctx->opcode, 11, 3));
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break;
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case NM_SEB:
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check_nms(ctx);
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gen_bshfl(ctx, OPC_SEB, rs, rt);
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break;
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case NM_SEH:
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@ -17153,6 +17168,7 @@ static void gen_pool32a0_nanomips_insn(CPUMIPSState *env, DisasContext *ctx)
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gen_arith(ctx, OPC_ADDU, rd, rs, rt);
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break;
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case NM_SUB:
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check_nms(ctx);
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gen_arith(ctx, OPC_SUB, rd, rs, rt);
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break;
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case NM_SUBU:
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@ -18019,9 +18035,11 @@ static void gen_pool32axf_4_nanomips_insn(DisasContext *ctx, uint32_t opc,
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gen_bitswap(ctx, OPC_BITSWAP, ret, rs);
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break;
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case NM_CLO:
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check_nms(ctx);
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gen_cl(ctx, OPC_CLO, ret, rs);
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break;
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case NM_CLZ:
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check_nms(ctx);
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gen_cl(ctx, OPC_CLZ, ret, rs);
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break;
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case NM_WSBH:
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@ -18227,6 +18245,7 @@ static void gen_compute_imm_branch(DisasContext *ctx, uint32_t opc,
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break;
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case NM_BBEQZC:
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case NM_BBNEZC:
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check_nms(ctx);
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if (imm >= 32 && !(ctx->hflags & MIPS_HFLAG_64)) {
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generate_exception_end(ctx, EXCP_RI);
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goto out;
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@ -18531,13 +18550,15 @@ static void gen_p_lsx(DisasContext *ctx, int rd, int rs, int rt)
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if ((extract32(ctx->opcode, 6, 1)) == 1) {
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/* PP.LSXS instructions require shifting */
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switch (extract32(ctx->opcode, 7, 4)) {
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case NM_LHXS:
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case NM_SHXS:
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check_nms(ctx);
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case NM_LHXS:
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case NM_LHUXS:
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tcg_gen_shli_tl(tcg_ctx, t0, t0, 1);
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break;
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case NM_LWXS:
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case NM_SWXS:
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check_nms(ctx);
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case NM_LWXS:
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case NM_LWC1XS:
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case NM_SWC1XS:
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tcg_gen_shli_tl(tcg_ctx, t0, t0, 2);
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@ -18580,18 +18601,21 @@ static void gen_p_lsx(DisasContext *ctx, int rd, int rs, int rt)
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gen_store_gpr(tcg_ctx, t0, rd);
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break;
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case NM_SBX:
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check_nms(ctx);
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gen_load_gpr(ctx, t1, rd);
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tcg_gen_qemu_st_tl(ctx->uc, t1, t0, ctx->mem_idx,
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MO_8);
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break;
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case NM_SHX:
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/*case NM_SHXS:*/
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check_nms(ctx);
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gen_load_gpr(ctx, t1, rd);
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tcg_gen_qemu_st_tl(ctx->uc, t1, t0, ctx->mem_idx,
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MO_TEUW);
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break;
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case NM_SWX:
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/*case NM_SWXS:*/
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check_nms(ctx);
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gen_load_gpr(ctx, t1, rd);
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tcg_gen_qemu_st_tl(ctx->uc, t1, t0, ctx->mem_idx,
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MO_TEUL);
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@ -19617,22 +19641,26 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
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target_long addr_off = extract32(ctx->opcode, 0, 16) | insn << 16;
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switch (extract32(ctx->opcode, 16, 5)) {
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case NM_LI48:
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check_nms(ctx);
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if (rt != 0) {
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tcg_gen_movi_tl(tcg_ctx, tcg_ctx->cpu_gpr[rt], addr_off);
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}
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break;
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case NM_ADDIU48:
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check_nms(ctx);
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if (rt != 0) {
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tcg_gen_addi_tl(tcg_ctx, tcg_ctx->cpu_gpr[rt], tcg_ctx->cpu_gpr[rt], addr_off);
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tcg_gen_ext32s_tl(tcg_ctx, tcg_ctx->cpu_gpr[rt], tcg_ctx->cpu_gpr[rt]);
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}
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break;
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case NM_ADDIUGP48:
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check_nms(ctx);
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if (rt != 0) {
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gen_op_addr_addi(ctx, tcg_ctx->cpu_gpr[rt], tcg_ctx->cpu_gpr[28], addr_off);
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}
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break;
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case NM_ADDIUPC48:
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check_nms(ctx);
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if (rt != 0) {
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target_long addr = addr_add(ctx, ctx->base.pc_next + 6,
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addr_off);
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@ -19641,6 +19669,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
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}
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break;
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case NM_LWPC48:
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check_nms(ctx);
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if (rt != 0) {
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TCGv t0;
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t0 = tcg_temp_new(tcg_ctx);
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@ -19654,6 +19683,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
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}
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break;
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case NM_SWPC48:
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check_nms(ctx);
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{
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TCGv t0, t1;
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t0 = tcg_temp_new(tcg_ctx);
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@ -19774,6 +19804,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
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}
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break;
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case NM_P_ROTX:
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check_nms(ctx);
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if (rt != 0) {
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TCGv t0 = tcg_temp_new(tcg_ctx);
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TCGv_i32 shift = tcg_const_i32(tcg_ctx, extract32(ctx->opcode, 0, 5));
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@ -19791,6 +19822,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
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}
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break;
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case NM_P_INS:
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check_nms(ctx);
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switch (((ctx->opcode >> 10) & 2) |
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(extract32(ctx->opcode, 5, 1))) {
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case NM_INS:
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@ -19806,6 +19838,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
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switch (((ctx->opcode >> 10) & 2) |
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(extract32(ctx->opcode, 5, 1))) {
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case NM_EXT:
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check_nms(ctx);
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gen_bitops(ctx, OPC_EXT, rt, rs, extract32(ctx->opcode, 0, 5),
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extract32(ctx->opcode, 6, 5));
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break;
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@ -20032,6 +20065,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
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switch (extract32(ctx->opcode, 11, 4)) {
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case NM_UALH:
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case NM_UASH:
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check_nms(ctx);
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{
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TCGv t0 = tcg_temp_new(tcg_ctx);
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TCGv t1 = tcg_temp_new(tcg_ctx);
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@ -20086,6 +20120,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
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break;
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case NM_P_LS_WM:
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case NM_P_LS_UAWM:
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check_nms(ctx);
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{
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int count = extract32(ctx->opcode, 12, 3);
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int counter = 0;
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@ -20134,6 +20169,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
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}
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break;
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case NM_MOVE_BALC:
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check_nms(ctx);
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{
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TCGv t0 = tcg_temp_new(tcg_ctx);
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int32_t s = sextract32(ctx->opcode, 0, 1) << 21 |
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@ -20181,6 +20217,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
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extract32(ctx->opcode, 1, 13) << 1;
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switch (extract32(ctx->opcode, 14, 2)) {
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case NM_BEQC:
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check_nms(ctx);
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gen_compute_branch_nm(ctx, OPC_BEQ, 4, rs, rt, s);
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break;
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case NM_P_BR3A:
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@ -20234,6 +20271,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
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extract32(ctx->opcode, 1, 13) << 1;
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switch (extract32(ctx->opcode, 14, 2)) {
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case NM_BNEC:
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check_nms(ctx);
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gen_compute_branch_nm(ctx, OPC_BNE, 4, rs, rt, s);
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break;
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case NM_BLTC:
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@ -20408,9 +20446,11 @@ static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx)
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switch ((extract32(ctx->opcode, 7, 2) & 0x2) |
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(extract32(ctx->opcode, 3, 1))) {
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case NM_ADDU4X4:
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check_nms(ctx);
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gen_arith(ctx, OPC_ADDU, rt, rs, rt);
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break;
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case NM_MUL4X4:
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check_nms(ctx);
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gen_r6_muldiv(ctx, R6_OPC_MUL, rt, rs, rt);
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break;
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default:
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@ -20476,6 +20516,7 @@ static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx)
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gen_ld(ctx, OPC_LW, rt, 29, offset);
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break;
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case NM_LW4X4:
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check_nms(ctx);
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rt = (extract32(ctx->opcode, 9, 1) << 3) |
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extract32(ctx->opcode, 5, 3);
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rs = (extract32(ctx->opcode, 4, 1) << 3) |
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@ -20487,6 +20528,7 @@ static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx)
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gen_ld(ctx, OPC_LW, rt, rs, offset);
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break;
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case NM_SW4X4:
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check_nms(ctx);
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rt = (extract32(ctx->opcode, 9, 1) << 3) |
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extract32(ctx->opcode, 5, 3);
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rs = (extract32(ctx->opcode, 4, 1) << 3) |
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@ -20585,6 +20627,7 @@ static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx)
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case NM_MOVEP:
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break;
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case NM_MOVEPREV:
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check_nms(ctx);
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{
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static const int gpr2reg1[] = {4, 5, 6, 7};
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static const int gpr2reg2[] = {5, 6, 7, 8};
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