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target-mips: replace MIPS64R6-generic with the real I6400 CPU model
MIPS64R6-generic gradually gets closer to I6400 CPU, feature-wise. Rename it to make it clear which MIPS processor it is supposed to emulate. Backports commit 8f95ad1c79b4166350b982a6defe0e21faa04dac from qemu
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@ -814,25 +814,22 @@ static const mips_def_t mips_defs[] =
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MMU_TYPE_R4000,
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},
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{
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/* A generic CPU supporting MIPS64 Release 6 ISA.
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FIXME: Support IEEE 754-2008 FP and misaligned memory accesses.
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Eventually this should be replaced by a real CPU model. */
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"MIPS64R6-generic",
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0x00010000,
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"I6400",
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0x1A900,
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MIPS_CONFIG0 | (0x2 << CP0C0_AR) | (0x2 << CP0C0_AT) |
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(MMU_TYPE_R4000 << CP0C0_MT),
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MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) |
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(2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
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(2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
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MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
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(2 << CP0C1_IS) | (5 << CP0C1_IL) | (3 << CP0C1_IA) |
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(2 << CP0C1_DS) | (5 << CP0C1_DL) | (3 << CP0C1_DA) |
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(0 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
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MIPS_CONFIG2,
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MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_CMGCR) | (1 << CP0C3_MSAP) |
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(1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_ULRI) |
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(1 << CP0C3_RXI) | (1 << CP0C3_LPA),
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(1 << CP0C3_RXI) | (1 << CP0C3_LPA) | (1 << CP0C3_VInt),
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MIPS_CONFIG4 | (1U << CP0C4_M) | (3 << CP0C4_IE) |
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(0xfc << CP0C4_KScrExist),
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MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_VP) |
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(1 << CP0C5_LLB),
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(1 << CP0C5_LLB) | (1 << CP0C5_MRP),
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(1 << CP0C5_MSAEn) | (1 << CP0C5_SBRI) |
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(1 << CP0C5_FRE) | (1 << CP0C5_UFE),
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0,
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@ -847,10 +844,10 @@ static const mips_def_t mips_defs[] =
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0,
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(1 << FCR0_FREP) | (1 << FCR0_HAS2008) | (1 << FCR0_F64) |
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(1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
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(1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
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(1 << FCR0_S) | (0x03 << FCR0_PRID) | (0x0 << FCR0_REV),
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0x0103FFFF,
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(1 << FCR31_ABS2008) | (1 << FCR31_NAN2008),
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0,
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0x03 << MSAIR_ProcID,
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48,
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48,
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0,0, 0,0, 0,0, 0,0, 0,0,
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