yuzu/unicorn
1
0
Fork 0
mirror of https://github.com/yuzu-emu/unicorn.git synced 2024-12-23 09:35:40 +00:00
Code Issues Packages Projects Releases Wiki Activity

tcg: fix s/compliment/complement/ typos

Browse source 
Backports commit 1d349821551c2da4dfefe36c6ac17319f33ebbd5 from qemu
This commit is contained in:
Emilio G. Cota 2018-05-22 00:29:39 -04:00 committed by Lioncash
parent 6835b2dd13
commit 7e8902eccc
No known key found for this signature in database
GPG key ID: 4E3C3CC1031BA9C7
3 changed files with 3 additions and 3 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
qemu/target/i386/translate.c
View file

@ -90,7 +90,7 @@ typedef struct DisasContext {
int rex_x, rex_b; int rex_x, rex_b;
#endif #endif
int vex_l; /* vex vector length */ int vex_l; /* vex vector length */
int vex_v; /* vex vvvv register, without 1's compliment. */ int vex_v; /* vex vvvv register, without 1's complement. */
int ss32; /* 32 bit stack segment */ int ss32; /* 32 bit stack segment */
CCOp cc_op; /* current CC operation */ CCOp cc_op; /* current CC operation */
CCOp last_cc_op; /* Unicorn: last CC operation. Save this to see if cc_op has changed */ CCOp last_cc_op; /* Unicorn: last CC operation. Save this to see if cc_op has changed */

2
qemu/target/m68k/translate.c
View file

@ -4171,7 +4171,7 @@ DISAS_INSN(bfext_reg)
TCGv shift; TCGv shift;
/* In general, we're going to rotate the field so that it's at the /* In general, we're going to rotate the field so that it's at the
top of the word and then right-shift by the compliment of the top of the word and then right-shift by the complement of the
width to extend the field. */ width to extend the field. */
if (ext & 0x20) { if (ext & 0x20) {
/* Variable width. */ /* Variable width. */

2
qemu/tcg/README
View file

@ -556,7 +556,7 @@ E.g. VECL=1 -> 64 << 1 -> v128, and VECE=2 -> 1 << 2 -> i32.
* orc_vec v0, v1, v2 * orc_vec v0, v1, v2
* not_vec v0, v1 * not_vec v0, v1
Similarly, logical operations with and without compliment. Similarly, logical operations with and without complement.
Note that VECE is unused. Note that VECE is unused.
* shli_vec v0, v1, i2 * shli_vec v0, v1, i2