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https://github.com/yuzu-emu/unicorn.git
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Revert "cputlb: Filter flushes on already clean tlbs"
This reverts commit 5ab9723787
.
This commit is contained in:
parent
576be63f06
commit
802c626145
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@ -64,10 +64,6 @@
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void tlb_init(CPUState *cpu)
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{
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CPUArchState *env = cpu->env_ptr;
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/* Ensure that cpu_reset performs a full flush. */
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env->tlb_c.dirty = ALL_MMUIDX_BITS;
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}
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static void tlb_flush_one_mmuidx_locked(CPUArchState *env, int mmu_idx)
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@ -82,19 +78,15 @@ static void tlb_flush_one_mmuidx_locked(CPUArchState *env, int mmu_idx)
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static void tlb_flush_by_mmuidx_async_work(CPUState *cpu, run_on_cpu_data data)
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{
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CPUArchState *env = cpu->env_ptr;
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uint16_t asked = data.host_int;
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uint16_t all_dirty, work, to_clean;
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unsigned long mmu_idx_bitmask = data.host_int;
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int mmu_idx;
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tlb_debug("mmu_idx:0x%04" PRIx16 "\n", asked);
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tlb_debug("mmu_idx:0x%04lx\n", mmu_idx_bitmask);
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all_dirty = env->tlb_c.dirty;
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to_clean = asked & all_dirty;
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all_dirty &= ~to_clean;
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env->tlb_c.dirty = all_dirty;
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for (work = to_clean; work != 0; work &= work - 1) {
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int mmu_idx = ctz32(work);
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tlb_flush_one_mmuidx_locked(env, mmu_idx);
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for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) {
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if (test_bit(mmu_idx, &mmu_idx_bitmask)) {
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tlb_flush_one_mmuidx_locked(env, mmu_idx);
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}
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}
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cpu_tb_jmp_cache_clear(cpu);
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@ -362,9 +354,10 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr,
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target_ulong address;
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target_ulong code_address;
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uintptr_t addend;
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CPUTLBEntry *te, tn;
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CPUTLBEntry *te;
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hwaddr iotlb, xlat, sz, paddr_page;
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target_ulong vaddr_page;
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unsigned vidx = env->tlb_d[mmu_idx].vindex++ % CPU_VTLB_SIZE;
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int asidx = cpu_asidx_from_attrs(cpu, attrs);
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if (size <= TARGET_PAGE_SIZE) {
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@ -409,24 +402,9 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr,
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index = tlb_index(env, mmu_idx, vaddr_page);
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te = tlb_entry(env, mmu_idx, vaddr_page);
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/* Note that the tlb is no longer clean. */
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env->tlb_c.dirty |= 1 << mmu_idx;
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/* Make sure there's no cached translation for the new page. */
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tlb_flush_vtlb_page_locked(env, mmu_idx, vaddr_page);
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/*
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* Only evict the old entry to the victim tlb if it's for a
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* different page; otherwise just overwrite the stale data.
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*/
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if (!tlb_hit_page_anyprot(te, vaddr_page)) {
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unsigned vidx = env->tlb_d[mmu_idx].vindex++ % CPU_VTLB_SIZE;
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CPUTLBEntry *tv = &env->tlb_v_table[mmu_idx][vidx];
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/* Evict the old entry into the victim tlb. */
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copy_tlb_helper_locked(tv, te);
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env->iotlb_v[mmu_idx][vidx] = env->iotlb[mmu_idx][index];
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}
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/* do not discard the translation in te, evict it into a victim tlb */
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env->tlb_v_table[mmu_idx][vidx] = *te;
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env->iotlb_v[mmu_idx][vidx] = env->iotlb[mmu_idx][index];
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/* refill the tlb */
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/*
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@ -443,39 +421,31 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr,
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*/
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env->iotlb[mmu_idx][index].addr = iotlb - vaddr_page;
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env->iotlb[mmu_idx][index].attrs = attrs;
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/* Now calculate the new entry */
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tn.addend = addend - vaddr_page;
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te->addend = addend - vaddr_page;
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if (prot & PAGE_READ) {
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tn.addr_read = address;
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te->addr_read = address;
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} else {
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tn.addr_read = -1;
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te->addr_read = -1;
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}
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if (prot & PAGE_EXEC) {
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tn.addr_code = code_address;
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te->addr_code = code_address;
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} else {
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tn.addr_code = -1;
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te->addr_code = -1;
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}
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tn.addr_write = -1;
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if (prot & PAGE_WRITE) {
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if ((memory_region_is_ram(section->mr) && section->readonly)
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|| memory_region_is_romd(section->mr)) {
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/* Write access calls the I/O callback. */
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tn.addr_write = address | TLB_MMIO;
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te->addr_write = address | TLB_MMIO;
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} else if (memory_region_is_ram(section->mr)) {
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tn.addr_write = address | TLB_NOTDIRTY;
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te->addr_write = address | TLB_NOTDIRTY;
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} else {
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tn.addr_write = address;
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}
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if (prot & PAGE_WRITE_INV) {
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tn.addr_write |= TLB_INVALID_MASK;
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te->addr_write = address;
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}
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} else {
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te->addr_write = -1;
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}
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copy_tlb_helper_locked(te, &tn);
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}
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/* Add a new TLB entry, but without specifying the memory
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@ -249,9 +249,6 @@ void address_space_stq_cached(MemoryRegionCache *cache, hwaddr addr, uint64_t va
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/* original state of the write flag (used when tracking self-modifying
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code */
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#define PAGE_WRITE_ORG 0x0010
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/* Invalidate the TLB entry immediately, helpful for s390x
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* Low-Address-Protection. Used with PAGE_WRITE in tlb_set_page_with_attrs() */
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#define PAGE_WRITE_INV 0x0040
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#if defined(CONFIG_BSD) && defined(CONFIG_USER_ONLY)
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/* FIXME: Code that sets/uses this is broken and needs to go away. */
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#define PAGE_RESERVED 0x0020
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@ -163,18 +163,6 @@ typedef struct CPUIOTLBEntry {
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MemTxAttrs attrs;
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} CPUIOTLBEntry;
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/*
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* Data elements that are shared between all MMU modes.
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*/
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typedef struct CPUTLBCommon {
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/*
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* Within dirty, for each bit N, modifications have been made to
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* mmu_idx N since the last time that mmu_idx was flushed.
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* Protected by tlb_c.lock.
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*/
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uint16_t dirty;
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} CPUTLBCommon;
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typedef struct CPUTLBDesc {
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/*
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* Describe a region covering all of the large pages allocated
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@ -188,13 +176,8 @@ typedef struct CPUTLBDesc {
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size_t vindex;
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} CPUTLBDesc;
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/*
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* The meaning of each of the MMU modes is defined in the target code.
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* Note that NB_MMU_MODES is not yet defined; we can only reference it
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* within preprocessor defines that will be expanded later.
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*/
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#define CPU_COMMON_TLB \
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CPUTLBCommon tlb_c; \
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/* The meaning of the MMU modes is defined in the target code. */ \
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CPUTLBDesc tlb_d[NB_MMU_MODES]; \
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CPUTLBEntry tlb_table[NB_MMU_MODES][CPU_TLB_SIZE]; \
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CPUTLBEntry tlb_v_table[NB_MMU_MODES][CPU_VTLB_SIZE]; \
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