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softfloat: Add round-to-odd rounding mode

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Power ISA 3.0 introduces a few quadruple precision floating point
instructions that support round-to-odd rounding mode. The
round-to-odd mode is explained as under:

Let Z be the intermediate arithmetic result or the operand of a convert
operation. If Z can be represented exactly in the target format, the
result is Z. Otherwise the result is either Z1 or Z2 whichever is odd.
Here Z1 and Z2 are the next larger and smaller numbers representable
in the target format respectively.

Backports commit 9ee6f678f473007e252934d6acd09c24490d9d42 from qemu
This commit is contained in:
Bharata B Rao 2018-03-02 08:24:49 -05:00 committed by Lioncash
parent 411ddd16cf
commit 80e522b499
No known key found for this signature in database
GPG key ID: 4E3C3CC1031BA9C7
2 changed files with 22 additions and 1 deletions
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21
qemu/fpu/softfloat.c
View file

@ -611,6 +611,9 @@ static float64 roundAndPackFloat64(flag zSign, int zExp, uint64_t zSig, float_st
case float_round_down:
roundIncrement = zSign ? 0x3ff : 0;
break;
case float_round_to_odd:
roundIncrement = (zSig & 0x400) ? 0 : 0x3ff;
break;
default:
abort();
}
@ -620,8 +623,10 @@ static float64 roundAndPackFloat64(flag zSign, int zExp, uint64_t zSig, float_st
|| ( ( zExp == 0x7FD )
&& ( (int64_t) ( zSig + roundIncrement ) < 0 ) )
) {
bool overflow_to_inf = roundingMode != float_round_to_odd &&
roundIncrement != 0;
float_raise(float_flag_overflow | float_flag_inexact, status);
return packFloat64( zSign, 0x7FF, - ( roundIncrement == 0 ));
return packFloat64(zSign, 0x7FF, -(!overflow_to_inf));
}
if ( zExp < 0 ) {
if (status->flush_to_zero) {
@ -638,6 +643,13 @@ static float64 roundAndPackFloat64(flag zSign, int zExp, uint64_t zSig, float_st
if (isTiny && roundBits) {
float_raise(float_flag_underflow, status);
}
if (roundingMode == float_round_to_odd) {
/*
* For round-to-odd case, the roundIncrement depends on
* zSig which just changed.
*/
roundIncrement = (zSig & 0x400) ? 0 : 0x3ff;
}
}
}
if ( roundBits ) status->float_exception_flags |= float_flag_inexact;
@ -1123,6 +1135,9 @@ static float128
case float_round_down:
increment = zSign && zSig2;
break;
case float_round_to_odd:
increment = !(zSig1 & 0x1) && zSig2;
break;
default:
abort();
}
@ -1142,6 +1157,7 @@ static float128
if ( ( roundingMode == float_round_to_zero )
|| ( zSign && ( roundingMode == float_round_up ) )
|| ( ! zSign && ( roundingMode == float_round_down ) )
|| (roundingMode == float_round_to_odd)
) {
return
packFloat128(
@ -1188,6 +1204,9 @@ static float128
case float_round_down:
increment = zSign && zSig2;
break;
case float_round_to_odd:
increment = !(zSig1 & 0x1) && zSig2;
break;
default:
abort();
}

2
qemu/include/fpu/softfloat.h
View file

@ -188,6 +188,8 @@ enum {
float_round_up = 2,
float_round_to_zero = 3,
float_round_ties_away = 4,
/* Not an IEEE rounding mode: round to the closest odd mantissa value */
float_round_to_odd = 5,
};
/*----------------------------------------------------------------------------