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https://github.com/yuzu-emu/unicorn.git
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target/riscv: Prevent lost illegal instruction exceptions
When decode_insn16() fails, we fall back to decode_RV32_64C() for further compressed instruction decoding. However, prior to this change, we did not raise an illegal instruction exception, if decode_RV32_64C() fails to decode the instruction. This means that we skipped illegal compressed instructions instead of raising an illegal instruction exception. Instead of patching decode_RV32_64C(), we can just remove it, as it is dead code since f330433b363 anyway. Backports 9a27f69bd668d9d71674407badc412ce1231c7d5
This commit is contained in:
Georg Kotheimer
Lioncash
parent
a1edab5abf
commit
83116e69b5
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@ -67,22 +67,6 @@ typedef struct DisasContext {
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struct uc_struct *uc;
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} DisasContext;
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#ifdef TARGET_RISCV64
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/* convert riscv funct3 to qemu memop for load/store */
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static const int tcg_memop_lookup[8] = {
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[0 ... 7] = -1,
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[0] = MO_SB,
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[1] = MO_TESW,
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[2] = MO_TESL,
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[4] = MO_UB,
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[5] = MO_TEUW,
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#ifdef TARGET_RISCV64
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[3] = MO_TEQ,
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[6] = MO_TEUL,
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#endif
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};
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#endif
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#ifdef TARGET_RISCV64
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#define CASE_OP_32_64(X) case X: case glue(X, W)
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#else
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@ -394,50 +378,6 @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
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ctx->base.is_jmp = DISAS_NORETURN;
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}
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#ifdef TARGET_RISCV64
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static void gen_load_c(DisasContext *ctx, uint32_t opc, int rd, int rs1,
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target_long imm)
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{
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TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
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TCGv t0 = tcg_temp_new(tcg_ctx);
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TCGv t1 = tcg_temp_new(tcg_ctx);
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gen_get_gpr(ctx, t0, rs1);
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tcg_gen_addi_tl(tcg_ctx, t0, t0, imm);
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int memop = tcg_memop_lookup[(opc >> 12) & 0x7];
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if (memop < 0) {
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gen_exception_illegal(ctx);
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return;
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}
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tcg_gen_qemu_ld_tl(ctx->uc, t1, t0, ctx->mem_idx, memop);
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gen_set_gpr(ctx, rd, t1);
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tcg_temp_free(tcg_ctx, t0);
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tcg_temp_free(tcg_ctx, t1);
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}
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static void gen_store_c(DisasContext *ctx, uint32_t opc, int rs1, int rs2,
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target_long imm)
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{
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TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
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TCGv t0 = tcg_temp_new(tcg_ctx);
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TCGv dat = tcg_temp_new(tcg_ctx);
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gen_get_gpr(ctx, t0, rs1);
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tcg_gen_addi_tl(tcg_ctx, t0, t0, imm);
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gen_get_gpr(ctx, dat, rs2);
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int memop = tcg_memop_lookup[(opc >> 12) & 0x7];
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if (memop < 0) {
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gen_exception_illegal(ctx);
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return;
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}
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tcg_gen_qemu_st_tl(ctx->uc, dat, t0, ctx->mem_idx, memop);
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tcg_temp_free(tcg_ctx, t0);
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tcg_temp_free(tcg_ctx, dat);
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}
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#endif
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#ifndef CONFIG_USER_ONLY
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/* The states of mstatus_fs are:
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* 0 = disabled, 1 = initial, 2 = clean, 3 = dirty
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@ -470,85 +410,6 @@ static void mark_fs_dirty(DisasContext *ctx)
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static inline void mark_fs_dirty(DisasContext *ctx) { }
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#endif
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#if !defined(TARGET_RISCV64)
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static void gen_fp_load(DisasContext *ctx, uint32_t opc, int rd,
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int rs1, target_long imm)
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{
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TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
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TCGv t0;
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if (ctx->mstatus_fs == 0) {
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gen_exception_illegal(ctx);
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return;
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}
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t0 = tcg_temp_new(tcg_ctx);
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gen_get_gpr(ctx, t0, rs1);
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tcg_gen_addi_tl(tcg_ctx, t0, t0, imm);
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switch (opc) {
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case OPC_RISC_FLW:
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if (!has_ext(ctx, RVF)) {
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goto do_illegal;
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}
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tcg_gen_qemu_ld_i64(ctx->uc, tcg_ctx->cpu_fpr_risc[rd], t0, ctx->mem_idx, MO_TEUL);
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/* RISC-V requires NaN-boxing of narrower width floating point values */
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tcg_gen_ori_i64(tcg_ctx, tcg_ctx->cpu_fpr_risc[rd], tcg_ctx->cpu_fpr_risc[rd], 0xffffffff00000000ULL);
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break;
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case OPC_RISC_FLD:
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if (!has_ext(ctx, RVD)) {
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goto do_illegal;
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}
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tcg_gen_qemu_ld_i64(ctx->uc, tcg_ctx->cpu_fpr_risc[rd], t0, ctx->mem_idx, MO_TEQ);
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break;
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do_illegal:
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default:
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gen_exception_illegal(ctx);
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break;
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}
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tcg_temp_free(tcg_ctx, t0);
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mark_fs_dirty(ctx);
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}
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static void gen_fp_store(DisasContext *ctx, uint32_t opc, int rs1,
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int rs2, target_long imm)
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{
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TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
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TCGv t0;
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if (ctx->mstatus_fs == 0) {
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gen_exception_illegal(ctx);
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return;
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}
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t0 = tcg_temp_new(tcg_ctx);
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gen_get_gpr(ctx, t0, rs1);
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tcg_gen_addi_tl(tcg_ctx, t0, t0, imm);
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switch (opc) {
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case OPC_RISC_FSW:
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if (!has_ext(ctx, RVF)) {
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goto do_illegal;
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}
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tcg_gen_qemu_st_i64(ctx->uc, tcg_ctx->cpu_fpr_risc[rs2], t0, ctx->mem_idx, MO_TEUL);
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break;
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case OPC_RISC_FSD:
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if (!has_ext(ctx, RVD)) {
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goto do_illegal;
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}
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tcg_gen_qemu_st_i64(ctx->uc, tcg_ctx->cpu_fpr_risc[rs2], t0, ctx->mem_idx, MO_TEQ);
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break;
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do_illegal:
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default:
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gen_exception_illegal(ctx);
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break;
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}
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tcg_temp_free(tcg_ctx, t0);
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}
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#endif
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static void gen_set_rm(DisasContext *ctx, int rm)
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{
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TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
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@ -563,49 +424,6 @@ static void gen_set_rm(DisasContext *ctx, int rm)
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tcg_temp_free_i32(tcg_ctx, t0);
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}
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static void decode_RV32_64C0(DisasContext *ctx)
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{
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uint8_t funct3 = extract32(ctx->opcode, 13, 3);
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uint8_t rd_rs2 = GET_C_RS2S(ctx->opcode);
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uint8_t rs1s = GET_C_RS1S(ctx->opcode);
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switch (funct3) {
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case 3:
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#if defined(TARGET_RISCV64)
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/* C.LD(RV64/128) -> ld rd', offset[7:3](rs1')*/
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gen_load_c(ctx, OPC_RISC_LD, rd_rs2, rs1s,
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GET_C_LD_IMM(ctx->opcode));
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#else
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/* C.FLW (RV32) -> flw rd', offset[6:2](rs1')*/
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gen_fp_load(ctx, OPC_RISC_FLW, rd_rs2, rs1s,
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GET_C_LW_IMM(ctx->opcode));
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#endif
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break;
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case 7:
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#if defined(TARGET_RISCV64)
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/* C.SD (RV64/128) -> sd rs2', offset[7:3](rs1')*/
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gen_store_c(ctx, OPC_RISC_SD, rs1s, rd_rs2,
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GET_C_LD_IMM(ctx->opcode));
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#else
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/* C.FSW (RV32) -> fsw rs2', offset[6:2](rs1')*/
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gen_fp_store(ctx, OPC_RISC_FSW, rs1s, rd_rs2,
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GET_C_LW_IMM(ctx->opcode));
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#endif
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break;
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}
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}
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static void decode_RV32_64C(DisasContext *ctx)
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{
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uint8_t op = extract32(ctx->opcode, 0, 2);
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switch (op) {
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case 0:
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decode_RV32_64C0(ctx);
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break;
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}
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}
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static int ex_plus_1(DisasContext *ctx, int nf)
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{
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return nf + 1;
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@ -802,8 +620,7 @@ static void decode_opc(DisasContext *ctx)
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} else {
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ctx->pc_succ_insn = ctx->base.pc_next + 2;
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if (!decode_insn16(ctx, ctx->opcode)) {
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/* fall back to old decoder */
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decode_RV32_64C(ctx);
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gen_exception_illegal(ctx);
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}
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}
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} else {
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