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softfloat: Don't execute divdeu without power7

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The divdeu instruction was added to ISA 2.06 (Power7).
Exclude this block from older cpus.

Fixes: 27ae5109a2ba (softfloat: Specialize udiv_qrnnd for ppc64)

Backports commit 7370981bd1ef58b3c20ba8b83cc342d1c61bc773 from qemu
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Richard Henderson 2018-11-11 08:33:44 -05:00 committed by Lioncash
parent 0557899c8e
commit 834514c676
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1 changed files with 1 additions and 1 deletions
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qemu/fpu/softfloat-macros.h
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@ -647,7 +647,7 @@ static inline uint64_t udiv_qrnnd(uint64_t *r, uint64_t n1,
asm("dlgr %0, %1" : "+r"(n) : "r"(d));
*r = n >> 64;
return n;
#elif defined(_ARCH_PPC64)
#elif defined(_ARCH_PPC64) && defined(_ARCH_PWR7)
/* From Power ISA 3.0B, programming note for divdeu. */
uint64_t q1, q2, Q, r1, r2, R;
asm("divdeu %0,%2,%4; divdu %1,%3,%4"