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target/arm: Add arm_tlb_bti_gp
Introduce an lvalue macro to wrap target_tlb_bit0. Backports commit 149d3b31f3f0f7f9e1c3a77043450a95c7a7e93d from qemu
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@ -3251,6 +3251,19 @@ static inline uint64_t *aa64_vfp_qreg(CPUARMState *env, unsigned regno)
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/* Shared between translate-sve.c and sve_helper.c. */
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/* Shared between translate-sve.c and sve_helper.c. */
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extern const uint64_t pred_esz_masks[4];
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extern const uint64_t pred_esz_masks[4];
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/* Helper for the macros below, validating the argument type. */
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static inline MemTxAttrs *typecheck_memtxattrs(MemTxAttrs *x)
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{
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return x;
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}
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/*
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* Lvalue macros for ARM TLB bits that we must cache in the TCG TLB.
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* Using these should be a bit more self-documenting than using the
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* generic target bits directly.
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*/
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#define arm_tlb_bti_gp(x) (typecheck_memtxattrs(x)->target_tlb_bit0)
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/*
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/*
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* Naming convention for isar_feature functions:
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* Naming convention for isar_feature functions:
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* Functions which test 32-bit ID registers should have _aa32_ in
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* Functions which test 32-bit ID registers should have _aa32_ in
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@ -10850,7 +10850,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
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}
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}
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/* When in aarch64 mode, and BTI is enabled, remember GP in the IOTLB. */
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/* When in aarch64 mode, and BTI is enabled, remember GP in the IOTLB. */
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if (aarch64 && guarded && cpu_isar_feature(aa64_bti, cpu)) {
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if (aarch64 && guarded && cpu_isar_feature(aa64_bti, cpu)) {
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txattrs->target_tlb_bit0 = true;
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arm_tlb_bti_gp(txattrs) = true;
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}
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}
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if (cacheattrs != NULL) {
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if (cacheattrs != NULL) {
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@ -14746,7 +14746,7 @@ static bool is_guarded_page(CPUARMState *env, DisasContext *s)
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* table entry even for that case.
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* table entry even for that case.
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*/
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*/
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return (tlb_hit(entry->addr_code, addr) &&
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return (tlb_hit(entry->addr_code, addr) &&
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env->iotlb[mmu_idx][index].attrs.target_tlb_bit0);
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arm_tlb_bti_gp(&env->iotlb[mmu_idx][index].attrs));
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#endif
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#endif
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}
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}
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