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cast all the values to write to registers in uc_reg_write() to unsigned type. this fixes issue #98

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This commit is contained in:
Nguyen Anh Quynh 2015-09-04 11:17:08 +08:00
parent 2cdadf1720
commit 84e3b5c897
7 changed files with 133 additions and 133 deletions
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6
qemu/target-arm/unicorn_aarch64.c
View file

@ -67,15 +67,15 @@ int arm64_reg_write(struct uc_struct *uc, unsigned int regid, const void *value)
CPUState *mycpu = first_cpu; CPUState *mycpu = first_cpu;
if (regid >= UC_ARM64_REG_X0 && regid <= UC_ARM64_REG_X28) if (regid >= UC_ARM64_REG_X0 && regid <= UC_ARM64_REG_X28)
ARM_CPU(uc, mycpu)->env.xregs[regid - UC_ARM64_REG_X0] = *(int64_t *)value; ARM_CPU(uc, mycpu)->env.xregs[regid - UC_ARM64_REG_X0] = *(uint64_t *)value;
else { else {
switch(regid) { switch(regid) {
default: break; default: break;
case UC_ARM64_REG_X29: case UC_ARM64_REG_X29:
ARM_CPU(uc, mycpu)->env.xregs[29] = *(int64_t *)value; ARM_CPU(uc, mycpu)->env.xregs[29] = *(uint64_t *)value;
break; break;
case UC_ARM64_REG_X30: case UC_ARM64_REG_X30:
ARM_CPU(uc, mycpu)->env.xregs[30] = *(int64_t *)value; ARM_CPU(uc, mycpu)->env.xregs[30] = *(uint64_t *)value;
break; break;
case UC_ARM64_REG_PC: case UC_ARM64_REG_PC:
ARM_CPU(uc, mycpu)->env.pc = *(uint64_t *)value; ARM_CPU(uc, mycpu)->env.pc = *(uint64_t *)value;

8
qemu/target-arm/unicorn_arm.c
View file

@ -88,20 +88,20 @@ int arm_reg_write(struct uc_struct *uc, unsigned int regid, const void *value)
case UC_MODE_ARM: case UC_MODE_ARM:
case UC_MODE_THUMB: case UC_MODE_THUMB:
if (regid >= UC_ARM_REG_R0 && regid <= UC_ARM_REG_R12) if (regid >= UC_ARM_REG_R0 && regid <= UC_ARM_REG_R12)
ARM_CPU(uc, mycpu)->env.regs[regid - UC_ARM_REG_R0] = *(int32_t *)value; ARM_CPU(uc, mycpu)->env.regs[regid - UC_ARM_REG_R0] = *(uint32_t *)value;
else { else {
switch(regid) { switch(regid) {
//case UC_ARM_REG_SP: //case UC_ARM_REG_SP:
case UC_ARM_REG_R13: case UC_ARM_REG_R13:
ARM_CPU(uc, mycpu)->env.regs[13] = *(int32_t *)value; ARM_CPU(uc, mycpu)->env.regs[13] = *(uint32_t *)value;
break; break;
//case UC_ARM_REG_LR: //case UC_ARM_REG_LR:
case UC_ARM_REG_R14: case UC_ARM_REG_R14:
ARM_CPU(uc, mycpu)->env.regs[14] = *(int32_t *)value; ARM_CPU(uc, mycpu)->env.regs[14] = *(uint32_t *)value;
break; break;
//case UC_ARM_REG_PC: //case UC_ARM_REG_PC:
case UC_ARM_REG_R15: case UC_ARM_REG_R15:
ARM_CPU(uc, mycpu)->env.regs[15] = *(int32_t *)value; ARM_CPU(uc, mycpu)->env.regs[15] = *(uint32_t *)value;
break; break;
} }
} }

240
qemu/target-i386/unicorn.c
View file

@ -552,19 +552,19 @@ int x86_reg_write(struct uc_struct *uc, unsigned int regid, const void *value)
switch(regid) { switch(regid) {
default: break; default: break;
case UC_X86_REG_ES: case UC_X86_REG_ES:
X86_CPU(uc, mycpu)->env.segs[R_ES].selector = *(int16_t *)value; X86_CPU(uc, mycpu)->env.segs[R_ES].selector = *(uint16_t *)value;
return 0; return 0;
case UC_X86_REG_SS: case UC_X86_REG_SS:
X86_CPU(uc, mycpu)->env.segs[R_SS].selector = *(int16_t *)value; X86_CPU(uc, mycpu)->env.segs[R_SS].selector = *(uint16_t *)value;
return 0; return 0;
case UC_X86_REG_DS: case UC_X86_REG_DS:
X86_CPU(uc, mycpu)->env.segs[R_DS].selector = *(int16_t *)value; X86_CPU(uc, mycpu)->env.segs[R_DS].selector = *(uint16_t *)value;
return 0; return 0;
case UC_X86_REG_FS: case UC_X86_REG_FS:
X86_CPU(uc, mycpu)->env.segs[R_FS].selector = *(int16_t *)value; X86_CPU(uc, mycpu)->env.segs[R_FS].selector = *(uint16_t *)value;
return 0; return 0;
case UC_X86_REG_GS: case UC_X86_REG_GS:
X86_CPU(uc, mycpu)->env.segs[R_GS].selector = *(int16_t *)value; X86_CPU(uc, mycpu)->env.segs[R_GS].selector = *(uint16_t *)value;
return 0; return 0;
} }
// fall-thru // fall-thru
@ -573,109 +573,109 @@ int x86_reg_write(struct uc_struct *uc, unsigned int regid, const void *value)
default: default:
break; break;
case UC_X86_REG_CR0 ... UC_X86_REG_CR4: case UC_X86_REG_CR0 ... UC_X86_REG_CR4:
X86_CPU(uc, mycpu)->env.cr[regid - UC_X86_REG_CR0] = *(int32_t *)value; X86_CPU(uc, mycpu)->env.cr[regid - UC_X86_REG_CR0] = *(uint32_t *)value;
break; break;
case UC_X86_REG_DR0 ... UC_X86_REG_DR7: case UC_X86_REG_DR0 ... UC_X86_REG_DR7:
X86_CPU(uc, mycpu)->env.dr[regid - UC_X86_REG_DR0] = *(int32_t *)value; X86_CPU(uc, mycpu)->env.dr[regid - UC_X86_REG_DR0] = *(uint32_t *)value;
break; break;
case UC_X86_REG_EFLAGS: case UC_X86_REG_EFLAGS:
X86_CPU(uc, mycpu)->env.eflags = *(int32_t *)value; X86_CPU(uc, mycpu)->env.eflags = *(uint32_t *)value;
break; break;
case UC_X86_REG_EAX: case UC_X86_REG_EAX:
X86_CPU(uc, mycpu)->env.regs[R_EAX] = *(int32_t *)value; X86_CPU(uc, mycpu)->env.regs[R_EAX] = *(uint32_t *)value;
break; break;
case UC_X86_REG_AX: case UC_X86_REG_AX:
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[R_EAX], *(int16_t *)value); WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[R_EAX], *(uint16_t *)value);
break; break;
case UC_X86_REG_AH: case UC_X86_REG_AH:
WRITE_BYTE_H(X86_CPU(uc, mycpu)->env.regs[R_EAX], *(int8_t *)value); WRITE_BYTE_H(X86_CPU(uc, mycpu)->env.regs[R_EAX], *(uint8_t *)value);
break; break;
case UC_X86_REG_AL: case UC_X86_REG_AL:
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_EAX], *(int8_t *)value); WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_EAX], *(uint8_t *)value);
break; break;
case UC_X86_REG_EBX: case UC_X86_REG_EBX:
X86_CPU(uc, mycpu)->env.regs[R_EBX] = *(int32_t *)value; X86_CPU(uc, mycpu)->env.regs[R_EBX] = *(uint32_t *)value;
break; break;
case UC_X86_REG_BX: case UC_X86_REG_BX:
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[R_EBX], *(int16_t *)value); WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[R_EBX], *(uint16_t *)value);
break; break;
case UC_X86_REG_BH: case UC_X86_REG_BH:
WRITE_BYTE_H(X86_CPU(uc, mycpu)->env.regs[R_EBX], *(int8_t *)value); WRITE_BYTE_H(X86_CPU(uc, mycpu)->env.regs[R_EBX], *(uint8_t *)value);
break; break;
case UC_X86_REG_BL: case UC_X86_REG_BL:
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_EBX], *(int8_t *)value); WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_EBX], *(uint8_t *)value);
break; break;
case UC_X86_REG_ECX: case UC_X86_REG_ECX:
X86_CPU(uc, mycpu)->env.regs[R_ECX] = *(int32_t *)value; X86_CPU(uc, mycpu)->env.regs[R_ECX] = *(uint32_t *)value;
break; break;
case UC_X86_REG_CX: case UC_X86_REG_CX:
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[R_ECX], *(int16_t *)value); WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[R_ECX], *(uint16_t *)value);
break; break;
case UC_X86_REG_CH: case UC_X86_REG_CH:
WRITE_BYTE_H(X86_CPU(uc, mycpu)->env.regs[R_ECX], *(int8_t *)value); WRITE_BYTE_H(X86_CPU(uc, mycpu)->env.regs[R_ECX], *(uint8_t *)value);
break; break;
case UC_X86_REG_CL: case UC_X86_REG_CL:
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_ECX], *(int8_t *)value); WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_ECX], *(uint8_t *)value);
break; break;
case UC_X86_REG_EDX: case UC_X86_REG_EDX:
X86_CPU(uc, mycpu)->env.regs[R_EDX] = *(int32_t *)value; X86_CPU(uc, mycpu)->env.regs[R_EDX] = *(uint32_t *)value;
break; break;
case UC_X86_REG_DX: case UC_X86_REG_DX:
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[R_EDX], *(int16_t *)value); WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[R_EDX], *(uint16_t *)value);
break; break;
case UC_X86_REG_DH: case UC_X86_REG_DH:
WRITE_BYTE_H(X86_CPU(uc, mycpu)->env.regs[R_EDX], *(int8_t *)value); WRITE_BYTE_H(X86_CPU(uc, mycpu)->env.regs[R_EDX], *(uint8_t *)value);
break; break;
case UC_X86_REG_DL: case UC_X86_REG_DL:
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_EDX], *(int8_t *)value); WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_EDX], *(uint8_t *)value);
break; break;
case UC_X86_REG_ESP: case UC_X86_REG_ESP:
X86_CPU(uc, mycpu)->env.regs[R_ESP] = *(int32_t *)value; X86_CPU(uc, mycpu)->env.regs[R_ESP] = *(uint32_t *)value;
break; break;
case UC_X86_REG_SP: case UC_X86_REG_SP:
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[R_ESP], *(int16_t *)value); WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[R_ESP], *(uint16_t *)value);
break; break;
case UC_X86_REG_EBP: case UC_X86_REG_EBP:
X86_CPU(uc, mycpu)->env.regs[R_EBP] = *(int32_t *)value; X86_CPU(uc, mycpu)->env.regs[R_EBP] = *(uint32_t *)value;
break; break;
case UC_X86_REG_BP: case UC_X86_REG_BP:
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[R_EBP], *(int16_t *)value); WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[R_EBP], *(uint16_t *)value);
break; break;
case UC_X86_REG_ESI: case UC_X86_REG_ESI:
X86_CPU(uc, mycpu)->env.regs[R_ESI] = *(int32_t *)value; X86_CPU(uc, mycpu)->env.regs[R_ESI] = *(uint32_t *)value;
break; break;
case UC_X86_REG_SI: case UC_X86_REG_SI:
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[R_ESI], *(int16_t *)value); WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[R_ESI], *(uint16_t *)value);
break; break;
case UC_X86_REG_EDI: case UC_X86_REG_EDI:
X86_CPU(uc, mycpu)->env.regs[R_EDI] = *(int32_t *)value; X86_CPU(uc, mycpu)->env.regs[R_EDI] = *(uint32_t *)value;
break; break;
case UC_X86_REG_DI: case UC_X86_REG_DI:
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[R_EDI], *(int16_t *)value); WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[R_EDI], *(uint16_t *)value);
break; break;
case UC_X86_REG_EIP: case UC_X86_REG_EIP:
X86_CPU(uc, mycpu)->env.eip = *(int32_t *)value; X86_CPU(uc, mycpu)->env.eip = *(uint32_t *)value;
break; break;
case UC_X86_REG_IP: case UC_X86_REG_IP:
WRITE_WORD(X86_CPU(uc, mycpu)->env.eip, *(int16_t *)value); WRITE_WORD(X86_CPU(uc, mycpu)->env.eip, *(uint16_t *)value);
break; break;
case UC_X86_REG_CS: case UC_X86_REG_CS:
X86_CPU(uc, mycpu)->env.segs[R_CS].base = *(int16_t *)value; X86_CPU(uc, mycpu)->env.segs[R_CS].base = *(uint16_t *)value;
break; break;
case UC_X86_REG_DS: case UC_X86_REG_DS:
X86_CPU(uc, mycpu)->env.segs[R_DS].base = *(int16_t *)value; X86_CPU(uc, mycpu)->env.segs[R_DS].base = *(uint16_t *)value;
break; break;
case UC_X86_REG_SS: case UC_X86_REG_SS:
X86_CPU(uc, mycpu)->env.segs[R_SS].base = *(int16_t *)value; X86_CPU(uc, mycpu)->env.segs[R_SS].base = *(uint16_t *)value;
break; break;
case UC_X86_REG_ES: case UC_X86_REG_ES:
X86_CPU(uc, mycpu)->env.segs[R_ES].base = *(int16_t *)value; X86_CPU(uc, mycpu)->env.segs[R_ES].base = *(uint16_t *)value;
break; break;
case UC_X86_REG_FS: case UC_X86_REG_FS:
X86_CPU(uc, mycpu)->env.segs[R_FS].base = *(int16_t *)value; X86_CPU(uc, mycpu)->env.segs[R_FS].base = *(uint16_t *)value;
break; break;
case UC_X86_REG_GS: case UC_X86_REG_GS:
X86_CPU(uc, mycpu)->env.segs[R_GS].base = *(int16_t *)value; X86_CPU(uc, mycpu)->env.segs[R_GS].base = *(uint16_t *)value;
break; break;
} }
break; break;
@ -686,244 +686,244 @@ int x86_reg_write(struct uc_struct *uc, unsigned int regid, const void *value)
default: default:
break; break;
case UC_X86_REG_CR0 ... UC_X86_REG_CR4: case UC_X86_REG_CR0 ... UC_X86_REG_CR4:
X86_CPU(uc, mycpu)->env.cr[regid - UC_X86_REG_CR0] = *(int64_t *)value; X86_CPU(uc, mycpu)->env.cr[regid - UC_X86_REG_CR0] = *(uint64_t *)value;
break; break;
case UC_X86_REG_DR0 ... UC_X86_REG_DR7: case UC_X86_REG_DR0 ... UC_X86_REG_DR7:
X86_CPU(uc, mycpu)->env.dr[regid - UC_X86_REG_DR0] = *(int64_t *)value; X86_CPU(uc, mycpu)->env.dr[regid - UC_X86_REG_DR0] = *(uint64_t *)value;
break; break;
case UC_X86_REG_EFLAGS: case UC_X86_REG_EFLAGS:
X86_CPU(uc, mycpu)->env.eflags = *(int64_t *)value; X86_CPU(uc, mycpu)->env.eflags = *(uint64_t *)value;
break; break;
case UC_X86_REG_RAX: case UC_X86_REG_RAX:
X86_CPU(uc, mycpu)->env.regs[R_EAX] = *(int64_t *)value; X86_CPU(uc, mycpu)->env.regs[R_EAX] = *(uint64_t *)value;
break; break;
case UC_X86_REG_EAX: case UC_X86_REG_EAX:
WRITE_DWORD(X86_CPU(uc, mycpu)->env.regs[R_EAX], *(int32_t *)value); WRITE_DWORD(X86_CPU(uc, mycpu)->env.regs[R_EAX], *(uint32_t *)value);
break; break;
case UC_X86_REG_AX: case UC_X86_REG_AX:
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[R_EAX], *(int16_t *)value); WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[R_EAX], *(uint16_t *)value);
break; break;
case UC_X86_REG_AH: case UC_X86_REG_AH:
WRITE_BYTE_H(X86_CPU(uc, mycpu)->env.regs[R_EAX], *(int8_t *)value); WRITE_BYTE_H(X86_CPU(uc, mycpu)->env.regs[R_EAX], *(uint8_t *)value);
break; break;
case UC_X86_REG_AL: case UC_X86_REG_AL:
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_EAX], *(int8_t *)value); WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_EAX], *(uint8_t *)value);
break; break;
case UC_X86_REG_RBX: case UC_X86_REG_RBX:
X86_CPU(uc, mycpu)->env.regs[R_EBX] = *(int64_t *)value; X86_CPU(uc, mycpu)->env.regs[R_EBX] = *(uint64_t *)value;
break; break;
case UC_X86_REG_EBX: case UC_X86_REG_EBX:
WRITE_DWORD(X86_CPU(uc, mycpu)->env.regs[R_EBX], *(int32_t *)value); WRITE_DWORD(X86_CPU(uc, mycpu)->env.regs[R_EBX], *(uint32_t *)value);
break; break;
case UC_X86_REG_BX: case UC_X86_REG_BX:
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[R_EBX], *(int16_t *)value); WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[R_EBX], *(uint16_t *)value);
break; break;
case UC_X86_REG_BH: case UC_X86_REG_BH:
WRITE_BYTE_H(X86_CPU(uc, mycpu)->env.regs[R_EBX], *(int8_t *)value); WRITE_BYTE_H(X86_CPU(uc, mycpu)->env.regs[R_EBX], *(uint8_t *)value);
break; break;
case UC_X86_REG_BL: case UC_X86_REG_BL:
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_EBX], *(int8_t *)value); WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_EBX], *(uint8_t *)value);
break; break;
case UC_X86_REG_RCX: case UC_X86_REG_RCX:
X86_CPU(uc, mycpu)->env.regs[R_ECX] = *(int64_t *)value; X86_CPU(uc, mycpu)->env.regs[R_ECX] = *(uint64_t *)value;
break; break;
case UC_X86_REG_ECX: case UC_X86_REG_ECX:
WRITE_DWORD(X86_CPU(uc, mycpu)->env.regs[R_ECX], *(int32_t *)value); WRITE_DWORD(X86_CPU(uc, mycpu)->env.regs[R_ECX], *(uint32_t *)value);
break; break;
case UC_X86_REG_CX: case UC_X86_REG_CX:
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[R_ECX], *(int16_t *)value); WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[R_ECX], *(uint16_t *)value);
break; break;
case UC_X86_REG_CH: case UC_X86_REG_CH:
WRITE_BYTE_H(X86_CPU(uc, mycpu)->env.regs[R_ECX], *(int8_t *)value); WRITE_BYTE_H(X86_CPU(uc, mycpu)->env.regs[R_ECX], *(uint8_t *)value);
break; break;
case UC_X86_REG_CL: case UC_X86_REG_CL:
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_ECX], *(int8_t *)value); WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_ECX], *(uint8_t *)value);
break; break;
case UC_X86_REG_RDX: case UC_X86_REG_RDX:
X86_CPU(uc, mycpu)->env.regs[R_EDX] = *(int64_t *)value; X86_CPU(uc, mycpu)->env.regs[R_EDX] = *(uint64_t *)value;
break; break;
case UC_X86_REG_EDX: case UC_X86_REG_EDX:
WRITE_DWORD(X86_CPU(uc, mycpu)->env.regs[R_EDX], *(int32_t *)value); WRITE_DWORD(X86_CPU(uc, mycpu)->env.regs[R_EDX], *(uint32_t *)value);
break; break;
case UC_X86_REG_DX: case UC_X86_REG_DX:
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[R_EDX], *(int16_t *)value); WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[R_EDX], *(uint16_t *)value);
break; break;
case UC_X86_REG_DH: case UC_X86_REG_DH:
WRITE_BYTE_H(X86_CPU(uc, mycpu)->env.regs[R_EDX], *(int8_t *)value); WRITE_BYTE_H(X86_CPU(uc, mycpu)->env.regs[R_EDX], *(uint8_t *)value);
break; break;
case UC_X86_REG_DL: case UC_X86_REG_DL:
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_EDX], *(int8_t *)value); WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_EDX], *(uint8_t *)value);
break; break;
case UC_X86_REG_RSP: case UC_X86_REG_RSP:
X86_CPU(uc, mycpu)->env.regs[R_ESP] = *(int64_t *)value; X86_CPU(uc, mycpu)->env.regs[R_ESP] = *(uint64_t *)value;
break; break;
case UC_X86_REG_ESP: case UC_X86_REG_ESP:
WRITE_DWORD(X86_CPU(uc, mycpu)->env.regs[R_ESP], *(int32_t *)value); WRITE_DWORD(X86_CPU(uc, mycpu)->env.regs[R_ESP], *(uint32_t *)value);
break; break;
case UC_X86_REG_SP: case UC_X86_REG_SP:
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[R_ESP], *(int16_t *)value); WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[R_ESP], *(uint16_t *)value);
break; break;
case UC_X86_REG_SPL: case UC_X86_REG_SPL:
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_ESP], *(int8_t *)value); WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_ESP], *(uint8_t *)value);
break; break;
case UC_X86_REG_RBP: case UC_X86_REG_RBP:
X86_CPU(uc, mycpu)->env.regs[R_EBP] = *(int64_t *)value; X86_CPU(uc, mycpu)->env.regs[R_EBP] = *(uint64_t *)value;
break; break;
case UC_X86_REG_EBP: case UC_X86_REG_EBP:
WRITE_DWORD(X86_CPU(uc, mycpu)->env.regs[R_EBP], *(int32_t *)value); WRITE_DWORD(X86_CPU(uc, mycpu)->env.regs[R_EBP], *(uint32_t *)value);
break; break;
case UC_X86_REG_BP: case UC_X86_REG_BP:
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[R_EBP], *(int16_t *)value); WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[R_EBP], *(uint16_t *)value);
break; break;
case UC_X86_REG_BPL: case UC_X86_REG_BPL:
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_EBP], *(int8_t *)value); WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_EBP], *(uint8_t *)value);
break; break;
case UC_X86_REG_RSI: case UC_X86_REG_RSI:
X86_CPU(uc, mycpu)->env.regs[R_ESI] = *(int64_t *)value; X86_CPU(uc, mycpu)->env.regs[R_ESI] = *(uint64_t *)value;
break; break;
case UC_X86_REG_ESI: case UC_X86_REG_ESI:
WRITE_DWORD(X86_CPU(uc, mycpu)->env.regs[R_ESI], *(int32_t *)value); WRITE_DWORD(X86_CPU(uc, mycpu)->env.regs[R_ESI], *(uint32_t *)value);
break; break;
case UC_X86_REG_SI: case UC_X86_REG_SI:
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[R_ESI], *(int16_t *)value); WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[R_ESI], *(uint16_t *)value);
break; break;
case UC_X86_REG_SIL: case UC_X86_REG_SIL:
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_ESI], *(int8_t *)value); WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_ESI], *(uint8_t *)value);
break; break;
case UC_X86_REG_RDI: case UC_X86_REG_RDI:
X86_CPU(uc, mycpu)->env.regs[R_EDI] = *(int64_t *)value; X86_CPU(uc, mycpu)->env.regs[R_EDI] = *(uint64_t *)value;
break; break;
case UC_X86_REG_EDI: case UC_X86_REG_EDI:
WRITE_DWORD(X86_CPU(uc, mycpu)->env.regs[R_EDI], *(int32_t *)value); WRITE_DWORD(X86_CPU(uc, mycpu)->env.regs[R_EDI], *(uint32_t *)value);
break; break;
case UC_X86_REG_DI: case UC_X86_REG_DI:
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[R_EDI], *(int16_t *)value); WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[R_EDI], *(uint16_t *)value);
break; break;
case UC_X86_REG_DIL: case UC_X86_REG_DIL:
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_EDI], *(int8_t *)value); WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_EDI], *(uint8_t *)value);
break; break;
case UC_X86_REG_RIP: case UC_X86_REG_RIP:
X86_CPU(uc, mycpu)->env.eip = *(int64_t *)value; X86_CPU(uc, mycpu)->env.eip = *(uint64_t *)value;
break; break;
case UC_X86_REG_EIP: case UC_X86_REG_EIP:
WRITE_DWORD(X86_CPU(uc, mycpu)->env.eip, *(int32_t *)value); WRITE_DWORD(X86_CPU(uc, mycpu)->env.eip, *(uint32_t *)value);
break; break;
case UC_X86_REG_IP: case UC_X86_REG_IP:
WRITE_WORD(X86_CPU(uc, mycpu)->env.eip, *(int16_t *)value); WRITE_WORD(X86_CPU(uc, mycpu)->env.eip, *(uint16_t *)value);
break; break;
case UC_X86_REG_CS: case UC_X86_REG_CS:
X86_CPU(uc, mycpu)->env.segs[R_CS].base = *(int16_t *)value; X86_CPU(uc, mycpu)->env.segs[R_CS].base = *(uint16_t *)value;
break; break;
case UC_X86_REG_DS: case UC_X86_REG_DS:
X86_CPU(uc, mycpu)->env.segs[R_DS].base = *(int16_t *)value; X86_CPU(uc, mycpu)->env.segs[R_DS].base = *(uint16_t *)value;
break; break;
case UC_X86_REG_SS: case UC_X86_REG_SS:
X86_CPU(uc, mycpu)->env.segs[R_SS].base = *(int16_t *)value; X86_CPU(uc, mycpu)->env.segs[R_SS].base = *(uint16_t *)value;
break; break;
case UC_X86_REG_ES: case UC_X86_REG_ES:
X86_CPU(uc, mycpu)->env.segs[R_ES].base = *(int16_t *)value; X86_CPU(uc, mycpu)->env.segs[R_ES].base = *(uint16_t *)value;
break; break;
case UC_X86_REG_FS: case UC_X86_REG_FS:
X86_CPU(uc, mycpu)->env.segs[R_FS].base = *(int16_t *)value; X86_CPU(uc, mycpu)->env.segs[R_FS].base = *(uint16_t *)value;
break; break;
case UC_X86_REG_GS: case UC_X86_REG_GS:
X86_CPU(uc, mycpu)->env.segs[R_GS].base = *(int16_t *)value; X86_CPU(uc, mycpu)->env.segs[R_GS].base = *(uint16_t *)value;
break; break;
case UC_X86_REG_R8: case UC_X86_REG_R8:
X86_CPU(uc, mycpu)->env.regs[8] = *(int64_t *)value; X86_CPU(uc, mycpu)->env.regs[8] = *(uint64_t *)value;
break; break;
case UC_X86_REG_R8D: case UC_X86_REG_R8D:
WRITE_DWORD(X86_CPU(uc, mycpu)->env.regs[8], *(int32_t *)value); WRITE_DWORD(X86_CPU(uc, mycpu)->env.regs[8], *(uint32_t *)value);
break; break;
case UC_X86_REG_R8W: case UC_X86_REG_R8W:
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[8], *(int16_t *)value); WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[8], *(uint16_t *)value);
break; break;
case UC_X86_REG_R8B: case UC_X86_REG_R8B:
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[8], *(int8_t *)value); WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[8], *(uint8_t *)value);
break; break;
case UC_X86_REG_R9: case UC_X86_REG_R9:
X86_CPU(uc, mycpu)->env.regs[9] = *(int64_t *)value; X86_CPU(uc, mycpu)->env.regs[9] = *(uint64_t *)value;
break; break;
case UC_X86_REG_R9D: case UC_X86_REG_R9D:
WRITE_DWORD(X86_CPU(uc, mycpu)->env.regs[9], *(int32_t *)value); WRITE_DWORD(X86_CPU(uc, mycpu)->env.regs[9], *(uint32_t *)value);
break; break;
case UC_X86_REG_R9W: case UC_X86_REG_R9W:
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[9], *(int16_t *)value); WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[9], *(uint16_t *)value);
break; break;
case UC_X86_REG_R9B: case UC_X86_REG_R9B:
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[9], *(int8_t *)value); WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[9], *(uint8_t *)value);
break; break;
case UC_X86_REG_R10: case UC_X86_REG_R10:
X86_CPU(uc, mycpu)->env.regs[10] = *(int64_t *)value; X86_CPU(uc, mycpu)->env.regs[10] = *(uint64_t *)value;
break; break;
case UC_X86_REG_R10D: case UC_X86_REG_R10D:
WRITE_DWORD(X86_CPU(uc, mycpu)->env.regs[10], *(int32_t *)value); WRITE_DWORD(X86_CPU(uc, mycpu)->env.regs[10], *(uint32_t *)value);
break; break;
case UC_X86_REG_R10W: case UC_X86_REG_R10W:
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[10], *(int16_t *)value); WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[10], *(uint16_t *)value);
break; break;
case UC_X86_REG_R10B: case UC_X86_REG_R10B:
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[10], *(int8_t *)value); WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[10], *(uint8_t *)value);
break; break;
case UC_X86_REG_R11: case UC_X86_REG_R11:
X86_CPU(uc, mycpu)->env.regs[11] = *(int64_t *)value; X86_CPU(uc, mycpu)->env.regs[11] = *(uint64_t *)value;
break; break;
case UC_X86_REG_R11D: case UC_X86_REG_R11D:
WRITE_DWORD(X86_CPU(uc, mycpu)->env.regs[11], *(int32_t *)value); WRITE_DWORD(X86_CPU(uc, mycpu)->env.regs[11], *(uint32_t *)value);
break; break;
case UC_X86_REG_R11W: case UC_X86_REG_R11W:
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[11], *(int16_t *)value); WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[11], *(uint16_t *)value);
break; break;
case UC_X86_REG_R11B: case UC_X86_REG_R11B:
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[11], *(int8_t *)value); WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[11], *(uint8_t *)value);
break; break;
case UC_X86_REG_R12: case UC_X86_REG_R12:
X86_CPU(uc, mycpu)->env.regs[12] = *(int64_t *)value; X86_CPU(uc, mycpu)->env.regs[12] = *(uint64_t *)value;
break; break;
case UC_X86_REG_R12D: case UC_X86_REG_R12D:
WRITE_DWORD(X86_CPU(uc, mycpu)->env.regs[12], *(int32_t *)value); WRITE_DWORD(X86_CPU(uc, mycpu)->env.regs[12], *(uint32_t *)value);
break; break;
case UC_X86_REG_R12W: case UC_X86_REG_R12W:
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[12], *(int16_t *)value); WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[12], *(uint16_t *)value);
break; break;
case UC_X86_REG_R12B: case UC_X86_REG_R12B:
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[12], *(int8_t *)value); WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[12], *(uint8_t *)value);
break; break;
case UC_X86_REG_R13: case UC_X86_REG_R13:
X86_CPU(uc, mycpu)->env.regs[13] = *(int64_t *)value; X86_CPU(uc, mycpu)->env.regs[13] = *(uint64_t *)value;
break; break;
case UC_X86_REG_R13D: case UC_X86_REG_R13D:
WRITE_DWORD(X86_CPU(uc, mycpu)->env.regs[13], *(int32_t *)value); WRITE_DWORD(X86_CPU(uc, mycpu)->env.regs[13], *(uint32_t *)value);
break; break;
case UC_X86_REG_R13W: case UC_X86_REG_R13W:
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[13], *(int16_t *)value); WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[13], *(uint16_t *)value);
break; break;
case UC_X86_REG_R13B: case UC_X86_REG_R13B:
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[13], *(int8_t *)value); WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[13], *(uint8_t *)value);
break; break;
case UC_X86_REG_R14: case UC_X86_REG_R14:
X86_CPU(uc, mycpu)->env.regs[14] = *(int64_t *)value; X86_CPU(uc, mycpu)->env.regs[14] = *(uint64_t *)value;
break; break;
case UC_X86_REG_R14D: case UC_X86_REG_R14D:
WRITE_DWORD(X86_CPU(uc, mycpu)->env.regs[14], *(int32_t *)value); WRITE_DWORD(X86_CPU(uc, mycpu)->env.regs[14], *(uint32_t *)value);
break; break;
case UC_X86_REG_R14W: case UC_X86_REG_R14W:
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[14], *(int16_t *)value); WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[14], *(uint16_t *)value);
break; break;
case UC_X86_REG_R14B: case UC_X86_REG_R14B:
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[14], *(int8_t *)value); WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[14], *(uint8_t *)value);
break; break;
case UC_X86_REG_R15: case UC_X86_REG_R15:
X86_CPU(uc, mycpu)->env.regs[15] = *(int64_t *)value; X86_CPU(uc, mycpu)->env.regs[15] = *(uint64_t *)value;
break; break;
case UC_X86_REG_R15D: case UC_X86_REG_R15D:
WRITE_DWORD(X86_CPU(uc, mycpu)->env.regs[15], *(int32_t *)value); WRITE_DWORD(X86_CPU(uc, mycpu)->env.regs[15], *(uint32_t *)value);
break; break;
case UC_X86_REG_R15W: case UC_X86_REG_R15W:
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[15], *(int16_t *)value); WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[15], *(uint16_t *)value);
break; break;
case UC_X86_REG_R15B: case UC_X86_REG_R15B:
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[15], *(int8_t *)value); WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[15], *(uint8_t *)value);
break; break;
} }
break; break;

4
qemu/target-m68k/unicorn.c
View file

@ -62,9 +62,9 @@ int m68k_reg_write(struct uc_struct *uc, unsigned int regid, const void *value)
CPUState *mycpu = first_cpu; CPUState *mycpu = first_cpu;
if (regid >= UC_M68K_REG_A0 && regid <= UC_M68K_REG_A7) if (regid >= UC_M68K_REG_A0 && regid <= UC_M68K_REG_A7)
M68K_CPU(uc, mycpu)->env.aregs[regid - UC_M68K_REG_A0] = *(int32_t *)value; M68K_CPU(uc, mycpu)->env.aregs[regid - UC_M68K_REG_A0] = *(uint32_t *)value;
else if (regid >= UC_M68K_REG_D0 && regid <= UC_M68K_REG_D7) else if (regid >= UC_M68K_REG_D0 && regid <= UC_M68K_REG_D7)
M68K_CPU(uc, mycpu)->env.dregs[regid - UC_M68K_REG_D0] = *(int32_t *)value; M68K_CPU(uc, mycpu)->env.dregs[regid - UC_M68K_REG_D0] = *(uint32_t *)value;
else { else {
switch(regid) { switch(regid) {
default: break; default: break;

4
qemu/target-mips/unicorn.c
View file

@ -60,12 +60,12 @@ int mips_reg_write(struct uc_struct *uc, unsigned int regid, const void *value)
CPUState *mycpu = first_cpu; CPUState *mycpu = first_cpu;
if (regid >= UC_MIPS_REG_0 && regid <= UC_MIPS_REG_31) if (regid >= UC_MIPS_REG_0 && regid <= UC_MIPS_REG_31)
MIPS_CPU(uc, mycpu)->env.active_tc.gpr[regid - UC_MIPS_REG_0] = *(int32_t *)value; MIPS_CPU(uc, mycpu)->env.active_tc.gpr[regid - UC_MIPS_REG_0] = *(uint32_t *)value;
else { else {
switch(regid) { switch(regid) {
default: break; default: break;
case UC_MIPS_REG_PC: case UC_MIPS_REG_PC:
MIPS_CPU(uc, mycpu)->env.active_tc.PC = *(int32_t *)value; MIPS_CPU(uc, mycpu)->env.active_tc.PC = *(uint32_t *)value;
break; break;
} }
} }

2
qemu/target-sparc/unicorn.c
View file

@ -73,7 +73,7 @@ int sparc_reg_write(struct uc_struct *uc, unsigned int regid, const void *value)
CPUState *mycpu = first_cpu; CPUState *mycpu = first_cpu;
if (regid >= UC_SPARC_REG_G0 && regid <= UC_SPARC_REG_G7) if (regid >= UC_SPARC_REG_G0 && regid <= UC_SPARC_REG_G7)
SPARC_CPU(uc, mycpu)->env.gregs[regid - UC_SPARC_REG_G0] = *(int32_t *)value; SPARC_CPU(uc, mycpu)->env.gregs[regid - UC_SPARC_REG_G0] = *(uint32_t *)value;
else { else {
switch(regid) { switch(regid) {
default: break; default: break;

2
qemu/target-sparc/unicorn64.c
View file

@ -56,7 +56,7 @@ int sparc_reg_write(struct uc_struct *uc, unsigned int regid, const void *value)
CPUState *mycpu = first_cpu; CPUState *mycpu = first_cpu;
if (regid >= UC_SPARC_REG_G0 && regid <= UC_SPARC_REG_G7) if (regid >= UC_SPARC_REG_G0 && regid <= UC_SPARC_REG_G7)
SPARC_CPU(uc, mycpu)->env.gregs[regid - UC_SPARC_REG_G0] = *(int32_t *)value; SPARC_CPU(uc, mycpu)->env.gregs[regid - UC_SPARC_REG_G0] = *(uint32_t *)value;
else { else {
switch(regid) { switch(regid) {
default: break; default: break;