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target/arm: Make cpu_register() available for other files

Browse source 
Make cpu_register() (renamed to arm_cpu_register()) available
from internals.h so we can register CPUs also from other files
in the future.

Backports commit 37bcf244454f4efb82e2c0c64bbd7eabcc165a0c from qemu
This commit is contained in:
Thomas Huth 2020-04-30 21:35:54 -04:00 committed by Lioncash
parent afeb8ff2dc
commit 84f2729a29
19 changed files with 44 additions and 15 deletions
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2
qemu/aarch64.h
View file

@ -27,6 +27,7 @@
#define aa64_generate_debug_exceptions aa64_generate_debug_exceptions_aarch64
#define aa64_zva_access aa64_zva_access_aarch64
#define aarch64_banked_spsr_index aarch64_banked_spsr_index_aarch64
#define aarch64_cpu_register aarch64_cpu_register_aarch64
#define aarch64_restore_sp aarch64_restore_sp_aarch64
#define aarch64_save_sp aarch64_save_sp_aarch64
#define aarch64_sync_32_to_64 aarch64_sync_32_to_64_aarch64
@ -148,6 +149,7 @@
#define arm_cpu_list arm_cpu_list_aarch64
#define arm_cpu_post_init arm_cpu_post_init_aarch64
#define arm_cpu_realizefn arm_cpu_realizefn_aarch64
#define arm_cpu_register arm_cpu_register_aarch64
#define arm_cpu_register_gdb_regs_for_features arm_cpu_register_gdb_regs_for_features_aarch64
#define arm_cpu_register_types arm_cpu_register_types_aarch64
#define arm_cpu_set_pc arm_cpu_set_pc_aarch64

2
qemu/aarch64eb.h
View file

@ -27,6 +27,7 @@
#define aa64_generate_debug_exceptions aa64_generate_debug_exceptions_aarch64eb
#define aa64_zva_access aa64_zva_access_aarch64eb
#define aarch64_banked_spsr_index aarch64_banked_spsr_index_aarch64eb
#define aarch64_cpu_register aarch64_cpu_register_aarch64eb
#define aarch64_restore_sp aarch64_restore_sp_aarch64eb
#define aarch64_save_sp aarch64_save_sp_aarch64eb
#define aarch64_sync_32_to_64 aarch64_sync_32_to_64_aarch64eb
@ -148,6 +149,7 @@
#define arm_cpu_list arm_cpu_list_aarch64eb
#define arm_cpu_post_init arm_cpu_post_init_aarch64eb
#define arm_cpu_realizefn arm_cpu_realizefn_aarch64eb
#define arm_cpu_register arm_cpu_register_aarch64eb
#define arm_cpu_register_gdb_regs_for_features arm_cpu_register_gdb_regs_for_features_aarch64eb
#define arm_cpu_register_types arm_cpu_register_types_aarch64eb
#define arm_cpu_set_pc arm_cpu_set_pc_aarch64eb

2
qemu/arm.h
View file

@ -27,6 +27,7 @@
#define aa64_generate_debug_exceptions aa64_generate_debug_exceptions_arm
#define aa64_zva_access aa64_zva_access_arm
#define aarch64_banked_spsr_index aarch64_banked_spsr_index_arm
#define aarch64_cpu_register aarch64_cpu_register_arm
#define aarch64_restore_sp aarch64_restore_sp_arm
#define aarch64_save_sp aarch64_save_sp_arm
#define aarch64_sync_32_to_64 aarch64_sync_32_to_64_arm
@ -148,6 +149,7 @@
#define arm_cpu_list arm_cpu_list_arm
#define arm_cpu_post_init arm_cpu_post_init_arm
#define arm_cpu_realizefn arm_cpu_realizefn_arm
#define arm_cpu_register arm_cpu_register_arm
#define arm_cpu_register_gdb_regs_for_features arm_cpu_register_gdb_regs_for_features_arm
#define arm_cpu_register_types arm_cpu_register_types_arm
#define arm_cpu_set_pc arm_cpu_set_pc_arm

2
qemu/armeb.h
View file

@ -27,6 +27,7 @@
#define aa64_generate_debug_exceptions aa64_generate_debug_exceptions_armeb
#define aa64_zva_access aa64_zva_access_armeb
#define aarch64_banked_spsr_index aarch64_banked_spsr_index_armeb
#define aarch64_cpu_register aarch64_cpu_register_armeb
#define aarch64_restore_sp aarch64_restore_sp_armeb
#define aarch64_save_sp aarch64_save_sp_armeb
#define aarch64_sync_32_to_64 aarch64_sync_32_to_64_armeb
@ -148,6 +149,7 @@
#define arm_cpu_list arm_cpu_list_armeb
#define arm_cpu_post_init arm_cpu_post_init_armeb
#define arm_cpu_realizefn arm_cpu_realizefn_armeb
#define arm_cpu_register arm_cpu_register_armeb
#define arm_cpu_register_gdb_regs_for_features arm_cpu_register_gdb_regs_for_features_armeb
#define arm_cpu_register_types arm_cpu_register_types_armeb
#define arm_cpu_set_pc arm_cpu_set_pc_armeb

2
qemu/header_gen.py
View file

@ -33,6 +33,7 @@ symbols = (
'aa64_generate_debug_exceptions',
'aa64_zva_access',
'aarch64_banked_spsr_index',
'aarch64_cpu_register',
'aarch64_restore_sp',
'aarch64_save_sp',
'aarch64_sync_32_to_64',
@ -154,6 +155,7 @@ symbols = (
'arm_cpu_list',
'arm_cpu_post_init',
'arm_cpu_realizefn',
'arm_cpu_register',
'arm_cpu_register_gdb_regs_for_features',
'arm_cpu_register_types',
'arm_cpu_set_pc',

2
qemu/m68k.h
View file

@ -27,6 +27,7 @@
#define aa64_generate_debug_exceptions aa64_generate_debug_exceptions_m68k
#define aa64_zva_access aa64_zva_access_m68k
#define aarch64_banked_spsr_index aarch64_banked_spsr_index_m68k
#define aarch64_cpu_register aarch64_cpu_register_m68k
#define aarch64_restore_sp aarch64_restore_sp_m68k
#define aarch64_save_sp aarch64_save_sp_m68k
#define aarch64_sync_32_to_64 aarch64_sync_32_to_64_m68k
@ -148,6 +149,7 @@
#define arm_cpu_list arm_cpu_list_m68k
#define arm_cpu_post_init arm_cpu_post_init_m68k
#define arm_cpu_realizefn arm_cpu_realizefn_m68k
#define arm_cpu_register arm_cpu_register_m68k
#define arm_cpu_register_gdb_regs_for_features arm_cpu_register_gdb_regs_for_features_m68k
#define arm_cpu_register_types arm_cpu_register_types_m68k
#define arm_cpu_set_pc arm_cpu_set_pc_m68k

2
qemu/mips.h
View file

@ -27,6 +27,7 @@
#define aa64_generate_debug_exceptions aa64_generate_debug_exceptions_mips
#define aa64_zva_access aa64_zva_access_mips
#define aarch64_banked_spsr_index aarch64_banked_spsr_index_mips
#define aarch64_cpu_register aarch64_cpu_register_mips
#define aarch64_restore_sp aarch64_restore_sp_mips
#define aarch64_save_sp aarch64_save_sp_mips
#define aarch64_sync_32_to_64 aarch64_sync_32_to_64_mips
@ -148,6 +149,7 @@
#define arm_cpu_list arm_cpu_list_mips
#define arm_cpu_post_init arm_cpu_post_init_mips
#define arm_cpu_realizefn arm_cpu_realizefn_mips
#define arm_cpu_register arm_cpu_register_mips
#define arm_cpu_register_gdb_regs_for_features arm_cpu_register_gdb_regs_for_features_mips
#define arm_cpu_register_types arm_cpu_register_types_mips
#define arm_cpu_set_pc arm_cpu_set_pc_mips

2
qemu/mips64.h
View file

@ -27,6 +27,7 @@
#define aa64_generate_debug_exceptions aa64_generate_debug_exceptions_mips64
#define aa64_zva_access aa64_zva_access_mips64
#define aarch64_banked_spsr_index aarch64_banked_spsr_index_mips64
#define aarch64_cpu_register aarch64_cpu_register_mips64
#define aarch64_restore_sp aarch64_restore_sp_mips64
#define aarch64_save_sp aarch64_save_sp_mips64
#define aarch64_sync_32_to_64 aarch64_sync_32_to_64_mips64
@ -148,6 +149,7 @@
#define arm_cpu_list arm_cpu_list_mips64
#define arm_cpu_post_init arm_cpu_post_init_mips64
#define arm_cpu_realizefn arm_cpu_realizefn_mips64
#define arm_cpu_register arm_cpu_register_mips64
#define arm_cpu_register_gdb_regs_for_features arm_cpu_register_gdb_regs_for_features_mips64
#define arm_cpu_register_types arm_cpu_register_types_mips64
#define arm_cpu_set_pc arm_cpu_set_pc_mips64

2
qemu/mips64el.h
View file

@ -27,6 +27,7 @@
#define aa64_generate_debug_exceptions aa64_generate_debug_exceptions_mips64el
#define aa64_zva_access aa64_zva_access_mips64el
#define aarch64_banked_spsr_index aarch64_banked_spsr_index_mips64el
#define aarch64_cpu_register aarch64_cpu_register_mips64el
#define aarch64_restore_sp aarch64_restore_sp_mips64el
#define aarch64_save_sp aarch64_save_sp_mips64el
#define aarch64_sync_32_to_64 aarch64_sync_32_to_64_mips64el
@ -148,6 +149,7 @@
#define arm_cpu_list arm_cpu_list_mips64el
#define arm_cpu_post_init arm_cpu_post_init_mips64el
#define arm_cpu_realizefn arm_cpu_realizefn_mips64el
#define arm_cpu_register arm_cpu_register_mips64el
#define arm_cpu_register_gdb_regs_for_features arm_cpu_register_gdb_regs_for_features_mips64el
#define arm_cpu_register_types arm_cpu_register_types_mips64el
#define arm_cpu_set_pc arm_cpu_set_pc_mips64el

2
qemu/mipsel.h
View file

@ -27,6 +27,7 @@
#define aa64_generate_debug_exceptions aa64_generate_debug_exceptions_mipsel
#define aa64_zva_access aa64_zva_access_mipsel
#define aarch64_banked_spsr_index aarch64_banked_spsr_index_mipsel
#define aarch64_cpu_register aarch64_cpu_register_mipsel
#define aarch64_restore_sp aarch64_restore_sp_mipsel
#define aarch64_save_sp aarch64_save_sp_mipsel
#define aarch64_sync_32_to_64 aarch64_sync_32_to_64_mipsel
@ -148,6 +149,7 @@
#define arm_cpu_list arm_cpu_list_mipsel
#define arm_cpu_post_init arm_cpu_post_init_mipsel
#define arm_cpu_realizefn arm_cpu_realizefn_mipsel
#define arm_cpu_register arm_cpu_register_mipsel
#define arm_cpu_register_gdb_regs_for_features arm_cpu_register_gdb_regs_for_features_mipsel
#define arm_cpu_register_types arm_cpu_register_types_mipsel
#define arm_cpu_set_pc arm_cpu_set_pc_mipsel

2
qemu/powerpc.h
View file

@ -27,6 +27,7 @@
#define aa64_generate_debug_exceptions aa64_generate_debug_exceptions_powerpc
#define aa64_zva_access aa64_zva_access_powerpc
#define aarch64_banked_spsr_index aarch64_banked_spsr_index_powerpc
#define aarch64_cpu_register aarch64_cpu_register_powerpc
#define aarch64_restore_sp aarch64_restore_sp_powerpc
#define aarch64_save_sp aarch64_save_sp_powerpc
#define aarch64_sync_32_to_64 aarch64_sync_32_to_64_powerpc
@ -148,6 +149,7 @@
#define arm_cpu_list arm_cpu_list_powerpc
#define arm_cpu_post_init arm_cpu_post_init_powerpc
#define arm_cpu_realizefn arm_cpu_realizefn_powerpc
#define arm_cpu_register arm_cpu_register_powerpc
#define arm_cpu_register_gdb_regs_for_features arm_cpu_register_gdb_regs_for_features_powerpc
#define arm_cpu_register_types arm_cpu_register_types_powerpc
#define arm_cpu_set_pc arm_cpu_set_pc_powerpc

2
qemu/riscv32.h
View file

@ -27,6 +27,7 @@
#define aa64_generate_debug_exceptions aa64_generate_debug_exceptions_riscv32
#define aa64_zva_access aa64_zva_access_riscv32
#define aarch64_banked_spsr_index aarch64_banked_spsr_index_riscv32
#define aarch64_cpu_register aarch64_cpu_register_riscv32
#define aarch64_restore_sp aarch64_restore_sp_riscv32
#define aarch64_save_sp aarch64_save_sp_riscv32
#define aarch64_sync_32_to_64 aarch64_sync_32_to_64_riscv32
@ -148,6 +149,7 @@
#define arm_cpu_list arm_cpu_list_riscv32
#define arm_cpu_post_init arm_cpu_post_init_riscv32
#define arm_cpu_realizefn arm_cpu_realizefn_riscv32
#define arm_cpu_register arm_cpu_register_riscv32
#define arm_cpu_register_gdb_regs_for_features arm_cpu_register_gdb_regs_for_features_riscv32
#define arm_cpu_register_types arm_cpu_register_types_riscv32
#define arm_cpu_set_pc arm_cpu_set_pc_riscv32

2
qemu/riscv64.h
View file

@ -27,6 +27,7 @@
#define aa64_generate_debug_exceptions aa64_generate_debug_exceptions_riscv64
#define aa64_zva_access aa64_zva_access_riscv64
#define aarch64_banked_spsr_index aarch64_banked_spsr_index_riscv64
#define aarch64_cpu_register aarch64_cpu_register_riscv64
#define aarch64_restore_sp aarch64_restore_sp_riscv64
#define aarch64_save_sp aarch64_save_sp_riscv64
#define aarch64_sync_32_to_64 aarch64_sync_32_to_64_riscv64
@ -148,6 +149,7 @@
#define arm_cpu_list arm_cpu_list_riscv64
#define arm_cpu_post_init arm_cpu_post_init_riscv64
#define arm_cpu_realizefn arm_cpu_realizefn_riscv64
#define arm_cpu_register arm_cpu_register_riscv64
#define arm_cpu_register_gdb_regs_for_features arm_cpu_register_gdb_regs_for_features_riscv64
#define arm_cpu_register_types arm_cpu_register_types_riscv64
#define arm_cpu_set_pc arm_cpu_set_pc_riscv64

2
qemu/sparc.h
View file

@ -27,6 +27,7 @@
#define aa64_generate_debug_exceptions aa64_generate_debug_exceptions_sparc
#define aa64_zva_access aa64_zva_access_sparc
#define aarch64_banked_spsr_index aarch64_banked_spsr_index_sparc
#define aarch64_cpu_register aarch64_cpu_register_sparc
#define aarch64_restore_sp aarch64_restore_sp_sparc
#define aarch64_save_sp aarch64_save_sp_sparc
#define aarch64_sync_32_to_64 aarch64_sync_32_to_64_sparc
@ -148,6 +149,7 @@
#define arm_cpu_list arm_cpu_list_sparc
#define arm_cpu_post_init arm_cpu_post_init_sparc
#define arm_cpu_realizefn arm_cpu_realizefn_sparc
#define arm_cpu_register arm_cpu_register_sparc
#define arm_cpu_register_gdb_regs_for_features arm_cpu_register_gdb_regs_for_features_sparc
#define arm_cpu_register_types arm_cpu_register_types_sparc
#define arm_cpu_set_pc arm_cpu_set_pc_sparc

2
qemu/sparc64.h
View file

@ -27,6 +27,7 @@
#define aa64_generate_debug_exceptions aa64_generate_debug_exceptions_sparc64
#define aa64_zva_access aa64_zva_access_sparc64
#define aarch64_banked_spsr_index aarch64_banked_spsr_index_sparc64
#define aarch64_cpu_register aarch64_cpu_register_sparc64
#define aarch64_restore_sp aarch64_restore_sp_sparc64
#define aarch64_save_sp aarch64_save_sp_sparc64
#define aarch64_sync_32_to_64 aarch64_sync_32_to_64_sparc64
@ -148,6 +149,7 @@
#define arm_cpu_list arm_cpu_list_sparc64
#define arm_cpu_post_init arm_cpu_post_init_sparc64
#define arm_cpu_realizefn arm_cpu_realizefn_sparc64
#define arm_cpu_register arm_cpu_register_sparc64
#define arm_cpu_register_gdb_regs_for_features arm_cpu_register_gdb_regs_for_features_sparc64
#define arm_cpu_register_types arm_cpu_register_types_sparc64
#define arm_cpu_set_pc arm_cpu_set_pc_sparc64

9
qemu/target/arm/cpu-qom.h
View file

@ -48,6 +48,15 @@ typedef struct ARMCPUClass {
void (*parent_reset)(CPUState *cpu);
} ARMCPUClass;
typedef struct ARMCPUInfo {
const char *name;
void (*initfn)(struct uc_struct *uc, Object *obj, void *opaque);
void (*class_init)(struct uc_struct *uc, ObjectClass *oc, void *data);
} ARMCPUInfo;
void arm_cpu_register(struct uc_struct *uc, const ARMCPUInfo *info);
void aarch64_cpu_register(struct uc_struct *uc, const ARMCPUInfo *info);
typedef struct ARMCPU ARMCPU;
#define TYPE_AARCH64_CPU "aarch64-cpu"

10
qemu/target/arm/cpu.c
View file

@ -1926,12 +1926,6 @@ static void arm_max_initfn(struct uc_struct *uc, Object *obj, void *opaque)
#endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */
typedef struct ARMCPUInfo {
const char *name;
void (*initfn)(struct uc_struct *uc, Object *obj, void *opaque);
void (*class_init)(struct uc_struct *uc, ObjectClass *oc, void *data);
} ARMCPUInfo;
static const ARMCPUInfo arm_cpus[] = {
#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
{ .name = "arm926", .initfn = arm926_initfn },
@ -2027,7 +2021,7 @@ static void arm_cpu_class_init(struct uc_struct *uc, ObjectClass *oc, void *data
#endif
}
static void cpu_register(struct uc_struct *uc, const ARMCPUInfo *info)
void arm_cpu_register(struct uc_struct *uc, const ARMCPUInfo *info)
{
TypeInfo type_info = {
.parent = TYPE_ARM_CPU,
@ -2062,7 +2056,7 @@ void arm_cpu_register_types(void *opaque)
type_register(opaque, &arm_cpu_type_info);
while (info->name) {
cpu_register(opaque, info);
arm_cpu_register(opaque, info);
info++;
}
}

8
qemu/target/arm/cpu64.c
View file

@ -379,12 +379,6 @@ static void aarch64_max_initfn(struct uc_struct *uc, Object *obj, void *opaque)
cpu->sve_max_vq = ARM_MAX_VQ;
}
typedef struct ARMCPUInfo {
const char *name;
void (*initfn)(struct uc_struct *uc, Object *obj, void *opaque);
void (*class_init)(struct uc_struct *uc, ObjectClass *oc, void *data);
} ARMCPUInfo;
static const ARMCPUInfo aarch64_cpus[] = {
{ .name = "cortex-a57", .initfn = aarch64_a57_initfn },
{ .name = "cortex-a53", .initfn = aarch64_a53_initfn },
@ -415,7 +409,7 @@ static void aarch64_cpu_class_init(struct uc_struct *uc, ObjectClass *oc, void *
cc->cpu_exec_interrupt = arm_cpu_exec_interrupt;
}
static void aarch64_cpu_register(struct uc_struct *uc, const ARMCPUInfo *info)
void aarch64_cpu_register(struct uc_struct *uc, const ARMCPUInfo *info)
{
TypeInfo type_info = {
.parent = TYPE_AARCH64_CPU,

2
qemu/x86_64.h
View file

@ -27,6 +27,7 @@
#define aa64_generate_debug_exceptions aa64_generate_debug_exceptions_x86_64
#define aa64_zva_access aa64_zva_access_x86_64
#define aarch64_banked_spsr_index aarch64_banked_spsr_index_x86_64
#define aarch64_cpu_register aarch64_cpu_register_x86_64
#define aarch64_restore_sp aarch64_restore_sp_x86_64
#define aarch64_save_sp aarch64_save_sp_x86_64
#define aarch64_sync_32_to_64 aarch64_sync_32_to_64_x86_64
@ -148,6 +149,7 @@
#define arm_cpu_list arm_cpu_list_x86_64
#define arm_cpu_post_init arm_cpu_post_init_x86_64
#define arm_cpu_realizefn arm_cpu_realizefn_x86_64
#define arm_cpu_register arm_cpu_register_x86_64
#define arm_cpu_register_gdb_regs_for_features arm_cpu_register_gdb_regs_for_features_x86_64
#define arm_cpu_register_types arm_cpu_register_types_x86_64
#define arm_cpu_set_pc arm_cpu_set_pc_x86_64