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target-mips: fix bad shifts in {dextp|dextpdp}

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Fixed issues in the MIPSDSP64 instructions dextp and dextpdp.
Shifting can go out of 32 bit range.

https://bugs.launchpad.net/qemu/+bug/1631625

Backports commit e6e2784cacd4cfec149a7690976b9ff15e541c4d from qemu
This commit is contained in:
Yongbok Kim 2018-03-01 09:04:30 -05:00 committed by Lioncash
parent b5468b4b22
commit 8575514f4c
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 2 additions and 2 deletions
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4
qemu/target-mips/dsp_helper.c
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@ -3477,7 +3477,7 @@ target_ulong helper_dextp(target_ulong ac, target_ulong size, CPUMIPSState *env)
if (sub >= -1) {
temp = (tempB << (64 - len)) | (tempA >> len);
temp = temp & ((0x01 << (size + 1)) - 1);
temp = temp & ((1ULL << (size + 1)) - 1);
set_DSPControl_efi(0, env);
} else {
set_DSPControl_efi(1, env);
@ -3506,7 +3506,7 @@ target_ulong helper_dextpdp(target_ulong ac, target_ulong size,
if (sub >= -1) {
temp = (tempB << (64 - len)) | (tempA >> len);
temp = temp & ((0x01 << (size + 1)) - 1);
temp = temp & ((1ULL << (size + 1)) - 1);
set_DSPControl_pos(sub, env);
set_DSPControl_efi(0, env);
} else {