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target-arm: Implement AArch32 ATS1H* operations

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Implement the AArch32 ATS1H* operations which perform
Hyp mode stage 1 translations.

Backports commit 14db7fe09a2c8d561ff37f98b328409906a560d7 from qemu
This commit is contained in:
Peter Maydell 2018-02-15 09:27:22 -05:00 committed by Lioncash
parent cf386519d2
commit 86af3f249d
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 22 additions and 0 deletions
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22
qemu/target-arm/helper.c
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@ -1597,6 +1597,17 @@ static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
A32_BANKED_CURRENT_REG_SET(env, par, par64);
}
static void ats1h_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
int access_type = ri->opc2 & 1;
uint64_t par64;
par64 = do_ats_write(env, value, access_type, ARMMMUIdx_S2NS);
A32_BANKED_CURRENT_REG_SET(env, par, par64);
}
static CPAccessResult at_s1e2_access(CPUARMState *env, const ARMCPRegInfo *ri)
{
if (arm_current_el(env) == 3 && !(env->cp15.scr_el3 & SCR_NS)) {
@ -2636,6 +2647,17 @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
{ "AT_S1E2W", 0,7,8, 1,4,1, ARM_CP_STATE_AA64, ARM_CP_NO_RAW,
PL2_W, 0, NULL, 0, 0, {0, 0},
at_s1e2_access, NULL, ats_write64 },
/* The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE
* if EL2 is not implemented; we choose to UNDEF. Behaviour at EL3
* with SCR.NS == 0 outside Monitor mode is UNPREDICTABLE; we choose
* to behave as if SCR.NS was 1.
*/
{ "ATS1HR", 15,7,8, 0,4,0, 0, ARM_CP_NO_RAW,
PL2_W, 0, NULL, 0, 0, {0, 0},
NULL, NULL, ats1h_write },
{ "ATS1HW", 15,7,8, 0,4,1, 0, ARM_CP_NO_RAW,
PL2_W, 0, NULL, 0, 0, {0, 0},
NULL, NULL, ats1h_write },
/* ARMv7 requires bit 0 and 1 to reset to 1. ARMv8 defines the
* reset values as IMPDEF. We choose to reset to 3 to comply with
* both ARMv7 and ARMv8.