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target/arm: Fix offset for LD1R instructions

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The immediate should be scaled by the size of the memory reference,
not the size of the elements into which it is loaded.

Backports commit d0e372b0298f897993f831dbff7ad4f1c70f138e from qemu
This commit is contained in:
Richard Henderson 2018-08-17 13:49:37 -04:00 committed by Lioncash
parent 7487c66bee
commit 86d6bb4d43
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 2 additions and 1 deletions
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3
qemu/target/arm/translate-sve.c
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@ -4993,6 +4993,7 @@ static bool trans_LD1R_zpri(DisasContext *s, arg_rpri_load *a, uint32_t insn)
unsigned vsz = vec_full_reg_size(s);
unsigned psz = pred_full_reg_size(s);
unsigned esz = dtype_esz[a->dtype];
unsigned msz = dtype_msz(a->dtype);
TCGLabel *over = gen_new_label(tcg_ctx);
TCGv_i64 temp;
@ -5016,7 +5017,7 @@ static bool trans_LD1R_zpri(DisasContext *s, arg_rpri_load *a, uint32_t insn)
/* Load the data. */
temp = tcg_temp_new_i64(tcg_ctx);
tcg_gen_addi_i64(tcg_ctx, temp, cpu_reg_sp(s, a->rn), a->imm << esz);
tcg_gen_addi_i64(tcg_ctx, temp, cpu_reg_sp(s, a->rn), a->imm << msz);
tcg_gen_qemu_ld_i64(s->uc, temp, temp, get_mem_index(s),
s->be_data | dtype_mop[a->dtype]);