mirror of
https://github.com/yuzu-emu/unicorn.git
synced 2024-12-22 19:45:35 +00:00
Fix uc_mode usage in source code
This commit is contained in:
parent
b7c43108bd
commit
8763d426c2
|
@ -75,7 +75,7 @@ int main(int argc, char **argv, char **envp)
|
|||
#endif
|
||||
|
||||
// Initialize emulator in MIPS 32bit little endian mode
|
||||
err = uc_open(UC_ARCH_MIPS, UC_MODE_MIPS32, &uc);
|
||||
err = uc_open(UC_ARCH_MIPS, UC_MODE_MIPS32 | UC_MODE_LITTLE_ENDIAN, &uc);
|
||||
if (err)
|
||||
{
|
||||
printf("Failed on uc_open() with error returned: %u\n", err);
|
||||
|
|
|
@ -14,11 +14,11 @@
|
|||
// These are masks of supported modes for each cpu/arch.
|
||||
// They should be updated when changes are made to the uc_mode enum typedef.
|
||||
#define UC_MODE_ARM_MASK (UC_MODE_ARM|UC_MODE_THUMB|UC_MODE_LITTLE_ENDIAN)
|
||||
#define UC_MODE_MIPS_MASK (UC_MODE_MICRO|UC_MODE_MIPS3|UC_MODE_MIPS32R6|UC_MODE_MIPS32|UC_MODE_MIPS64|UC_MODE_LITTLE_ENDIAN|UC_MODE_BIG_ENDIAN)
|
||||
#define UC_MODE_MIPS_MASK (UC_MODE_MIPS32|UC_MODE_MIPS64|UC_MODE_LITTLE_ENDIAN|UC_MODE_BIG_ENDIAN)
|
||||
#define UC_MODE_X86_MASK (UC_MODE_16|UC_MODE_32|UC_MODE_64|UC_MODE_LITTLE_ENDIAN)
|
||||
#define UC_MODE_PPC_MASK (UC_MODE_PPC64|UC_MODE_QPX|UC_MODE_LITTLE_ENDIAN)
|
||||
#define UC_MODE_SPARC_MASK (UC_MODE_V9|UC_MODE_LITTLE_ENDIAN)
|
||||
#define UC_MODE_M68K_MASK (UC_MODE_LITTLE_ENDIAN)
|
||||
#define UC_MODE_PPC_MASK (UC_MODE_PPC64|UC_MODE_BIG_ENDIAN)
|
||||
#define UC_MODE_SPARC_MASK (UC_MODE_SPARC64|UC_MODE_BIG_ENDIAN)
|
||||
#define UC_MODE_M68K_MASK (UC_MODE_BIG_ENDIAN)
|
||||
|
||||
#define ARR_SIZE(a) (sizeof(a)/sizeof(a[0]))
|
||||
|
||||
|
|
|
@ -87,16 +87,16 @@ typedef enum uc_arch {
|
|||
// Mode type
|
||||
typedef enum uc_mode {
|
||||
UC_MODE_LITTLE_ENDIAN = 0, // little-endian mode (default mode)
|
||||
UC_MODE_BIG_ENDIAN = 1 << 30, // big-endian mode (currently only supported by MIPS)
|
||||
UC_MODE_BIG_ENDIAN = 1 << 30, // big-endian mode
|
||||
// arm / arm64
|
||||
UC_MODE_ARM = 0, // 32-bit ARM
|
||||
UC_MODE_THUMB = 1 << 4, // ARM's Thumb mode, including Thumb-2
|
||||
UC_MODE_ARM = 0, // Start executing in ARM mode
|
||||
UC_MODE_THUMB = 1 << 4, // Start executing in THUMB mode (including Thumb-2)
|
||||
UC_MODE_MCLASS = 1 << 5, // ARM's Cortex-M series (currently unsupported)
|
||||
UC_MODE_V8 = 1 << 6, // ARMv8 A32 encodings for ARM (currently unsupported)
|
||||
// mips
|
||||
UC_MODE_MICRO = 1 << 4, // MicroMips mode
|
||||
UC_MODE_MIPS3 = 1 << 5, // Mips III ISA
|
||||
UC_MODE_MIPS32R6 = 1 << 6, // Mips32r6 ISA
|
||||
UC_MODE_MICRO = 1 << 4, // MicroMips mode (currently unsupported)
|
||||
UC_MODE_MIPS3 = 1 << 5, // Mips III ISA (currently unsupported)
|
||||
UC_MODE_MIPS32R6 = 1 << 6, // Mips32r6 ISA (currently unsupported)
|
||||
UC_MODE_MIPS32 = 1 << 2, // Mips32 ISA
|
||||
UC_MODE_MIPS64 = 1 << 3, // Mips64 ISA
|
||||
// x86 / x64
|
||||
|
@ -104,10 +104,11 @@ typedef enum uc_mode {
|
|||
UC_MODE_32 = 1 << 2, // 32-bit mode
|
||||
UC_MODE_64 = 1 << 3, // 64-bit mode
|
||||
// ppc
|
||||
UC_MODE_PPC64 = 1 << 3, // 64-bit mode
|
||||
UC_MODE_QPX = 1 << 4, // Quad Processing eXtensions mode
|
||||
UC_MODE_PPC64 = 1 << 3, // 64-bit mode (currently unsupported)
|
||||
UC_MODE_QPX = 1 << 4, // Quad Processing eXtensions mode (currently unsupported)
|
||||
// sparc
|
||||
UC_MODE_V9 = 1 << 4, // SparcV9 mode
|
||||
UC_MODE_SPARC64 = 1 << 3, // 64-bit mode
|
||||
UC_MODE_V9 = 1 << 4, // SparcV9 mode (currently unsupported)
|
||||
// m68k
|
||||
} uc_mode;
|
||||
|
||||
|
|
|
@ -42,36 +42,30 @@ int arm_reg_read(struct uc_struct *uc, unsigned int regid, void *value)
|
|||
|
||||
mycpu = first_cpu;
|
||||
|
||||
switch(uc->mode) {
|
||||
default:
|
||||
break;
|
||||
case UC_MODE_ARM:
|
||||
case UC_MODE_THUMB:
|
||||
if (regid >= UC_ARM_REG_R0 && regid <= UC_ARM_REG_R12)
|
||||
*(int32_t *)value = ARM_CPU(uc, mycpu)->env.regs[regid - UC_ARM_REG_R0];
|
||||
else {
|
||||
switch(regid) {
|
||||
case UC_ARM_REG_CPSR:
|
||||
*(int32_t *)value = cpsr_read(&ARM_CPU(uc, mycpu)->env);
|
||||
break;
|
||||
//case UC_ARM_REG_SP:
|
||||
case UC_ARM_REG_R13:
|
||||
*(int32_t *)value = ARM_CPU(uc, mycpu)->env.regs[13];
|
||||
break;
|
||||
//case UC_ARM_REG_LR:
|
||||
case UC_ARM_REG_R14:
|
||||
*(int32_t *)value = ARM_CPU(uc, mycpu)->env.regs[14];
|
||||
break;
|
||||
//case UC_ARM_REG_PC:
|
||||
case UC_ARM_REG_R15:
|
||||
*(int32_t *)value = ARM_CPU(uc, mycpu)->env.regs[15];
|
||||
break;
|
||||
}
|
||||
if (mode & ~UC_MODE_ARM_MASK) {
|
||||
if (regid >= UC_ARM_REG_R0 && regid <= UC_ARM_REG_R12)
|
||||
*(int32_t *)value = ARM_CPU(uc, mycpu)->env.regs[regid - UC_ARM_REG_R0];
|
||||
else {
|
||||
switch(regid) {
|
||||
case UC_ARM_REG_CPSR:
|
||||
*(int32_t *)value = cpsr_read(&ARM_CPU(uc, mycpu)->env);
|
||||
break;
|
||||
//case UC_ARM_REG_SP:
|
||||
case UC_ARM_REG_R13:
|
||||
*(int32_t *)value = ARM_CPU(uc, mycpu)->env.regs[13];
|
||||
break;
|
||||
//case UC_ARM_REG_LR:
|
||||
case UC_ARM_REG_R14:
|
||||
*(int32_t *)value = ARM_CPU(uc, mycpu)->env.regs[14];
|
||||
break;
|
||||
//case UC_ARM_REG_PC:
|
||||
case UC_ARM_REG_R15:
|
||||
*(int32_t *)value = ARM_CPU(uc, mycpu)->env.regs[15];
|
||||
break;
|
||||
}
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
@ -84,31 +78,25 @@ int arm_reg_write(struct uc_struct *uc, unsigned int regid, const void *value)
|
|||
{
|
||||
CPUState *mycpu = first_cpu;
|
||||
|
||||
switch(uc->mode) {
|
||||
default:
|
||||
break;
|
||||
|
||||
case UC_MODE_ARM:
|
||||
case UC_MODE_THUMB:
|
||||
if (regid >= UC_ARM_REG_R0 && regid <= UC_ARM_REG_R12)
|
||||
ARM_CPU(uc, mycpu)->env.regs[regid - UC_ARM_REG_R0] = *(uint32_t *)value;
|
||||
else {
|
||||
switch(regid) {
|
||||
//case UC_ARM_REG_SP:
|
||||
case UC_ARM_REG_R13:
|
||||
ARM_CPU(uc, mycpu)->env.regs[13] = *(uint32_t *)value;
|
||||
break;
|
||||
//case UC_ARM_REG_LR:
|
||||
case UC_ARM_REG_R14:
|
||||
ARM_CPU(uc, mycpu)->env.regs[14] = *(uint32_t *)value;
|
||||
break;
|
||||
//case UC_ARM_REG_PC:
|
||||
case UC_ARM_REG_R15:
|
||||
ARM_CPU(uc, mycpu)->env.regs[15] = *(uint32_t *)value;
|
||||
break;
|
||||
}
|
||||
if (mode & ~UC_MODE_ARM_MASK) {
|
||||
if (regid >= UC_ARM_REG_R0 && regid <= UC_ARM_REG_R12)
|
||||
ARM_CPU(uc, mycpu)->env.regs[regid - UC_ARM_REG_R0] = *(uint32_t *)value;
|
||||
else {
|
||||
switch(regid) {
|
||||
//case UC_ARM_REG_SP:
|
||||
case UC_ARM_REG_R13:
|
||||
ARM_CPU(uc, mycpu)->env.regs[13] = *(uint32_t *)value;
|
||||
break;
|
||||
//case UC_ARM_REG_LR:
|
||||
case UC_ARM_REG_R14:
|
||||
ARM_CPU(uc, mycpu)->env.regs[14] = *(uint32_t *)value;
|
||||
break;
|
||||
//case UC_ARM_REG_PC:
|
||||
case UC_ARM_REG_R15:
|
||||
ARM_CPU(uc, mycpu)->env.regs[15] = *(uint32_t *)value;
|
||||
break;
|
||||
}
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
|
|
@ -105,7 +105,7 @@ static void test_mips_el(void)
|
|||
printf("Emulate MIPS code (little-endian)\n");
|
||||
|
||||
// Initialize emulator in MIPS mode
|
||||
err = uc_open(UC_ARCH_MIPS, UC_MODE_MIPS32, &uc);
|
||||
err = uc_open(UC_ARCH_MIPS, UC_MODE_MIPS32 + UC_MODE_LITTLE_ENDIAN, &uc);
|
||||
if (err) {
|
||||
printf("Failed on uc_open() with error returned: %u (%s)\n",
|
||||
err, uc_strerror(err));
|
||||
|
|
|
@ -57,7 +57,7 @@ static void test_sparc(void)
|
|||
printf("Emulate SPARC code\n");
|
||||
|
||||
// Initialize emulator in Sparc mode
|
||||
err = uc_open(UC_ARCH_SPARC, UC_MODE_32, &uc);
|
||||
err = uc_open(UC_ARCH_SPARC, 0, &uc);
|
||||
if (err) {
|
||||
printf("Failed on uc_open() with error returned: %u (%s)\n",
|
||||
err, uc_strerror(err));
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
#include <unicorn/unicorn.h>
|
||||
|
||||
#define HARDWARE_ARCHITECTURE UC_ARCH_SPARC
|
||||
#define HARDWARE_MODE UC_MODE_32
|
||||
#define HARDWARE_MODE 0
|
||||
|
||||
#define MEMORY_STARTING_ADDRESS 0x1000000
|
||||
#define MEMORY_SIZE 2 * 1024 * 1024
|
||||
|
|
4
uc.c
4
uc.c
|
@ -190,7 +190,7 @@ uc_err uc_open(uc_arch arch, uc_mode mode, uc_engine **result)
|
|||
return UC_ERR_MODE;
|
||||
}
|
||||
|
||||
if (mode == UC_MODE_THUMB)
|
||||
if (mode & UC_MODE_THUMB)
|
||||
uc->thumb = 1;
|
||||
break;
|
||||
#endif
|
||||
|
@ -226,7 +226,7 @@ uc_err uc_open(uc_arch arch, uc_mode mode, uc_engine **result)
|
|||
|
||||
#ifdef UNICORN_HAS_SPARC
|
||||
case UC_ARCH_SPARC:
|
||||
if (mode & UC_MODE_64)
|
||||
if (mode & UC_MODE_SPARC64)
|
||||
uc->init_arch = sparc64_uc_init;
|
||||
else
|
||||
uc->init_arch = sparc_uc_init;
|
||||
|
|
Loading…
Reference in a new issue