yuzu/unicorn
1
0
Fork 0
mirror of https://github.com/yuzu-emu/unicorn.git synced 2025-07-04 04:18:14 +00:00
Code Issues Packages Projects Releases Wiki Activity

target/mips: Correct comments in translate.c

Browse source 
Fix some checkpatch comment-related warnings.

Backports commit 7480515fcc1b0f7119953d89e93b8507127aeb62 from qemu
This commit is contained in:
Aleksandar Markovic 2019-08-08 16:22:49 -04:00 committed by Lioncash
parent fa2a772c7b
commit 87edd2a82a
No known key found for this signature in database
GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 300 additions and 173 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

471
qemu/target/mips/translate.c
View file

@ -254,8 +254,10 @@ enum {
OPC_SPECIAL3D_RESERVED = 0x3D | OPC_SPECIAL, OPC_SPECIAL3D_RESERVED = 0x3D | OPC_SPECIAL,
}; };
/* R6 Multiply and Divide instructions have the same Opcode /*
and function field as legacy OPC_MULT[U]/OPC_DIV[U] */ * R6 Multiply and Divide instructions have the same opcode
* and function field as legacy OPC_MULT[U]/OPC_DIV[U]
*/
#define MASK_R6_MULDIV(op) (MASK_SPECIAL(op) | (op & (0x7ff))) #define MASK_R6_MULDIV(op) (MASK_SPECIAL(op) | (op & (0x7ff)))
enum { enum {
@ -2923,9 +2925,11 @@ static inline void check_cp1_enabled(DisasContext *ctx)
} }
} }
/* Verify that the processor is running with COP1X instructions enabled. /*
This is associated with the nabla symbol in the MIPS32 and MIPS64 * Verify that the processor is running with COP1X instructions enabled.
opcode tables. */ * This is associated with the nabla symbol in the MIPS32 and MIPS64
* opcode tables.
*/
static inline void check_cop1x(DisasContext *ctx) static inline void check_cop1x(DisasContext *ctx)
{ {
@ -2934,8 +2938,10 @@ static inline void check_cop1x(DisasContext *ctx)
} }
} }
/* Verify that the processor is running with 64-bit floating-point /*
operations enabled. */ * Verify that the processor is running with 64-bit floating-point
* operations enabled.
*/
static inline void check_cp1_64bitmode(DisasContext *ctx) static inline void check_cp1_64bitmode(DisasContext *ctx)
{ {
@ -2962,8 +2968,9 @@ static inline void check_cp1_registers(DisasContext *ctx, int regs)
} }
} }
/* Verify that the processor is running with DSP instructions enabled. /*
This is enabled by CP0 Status register MX(24) bit. * Verify that the processor is running with DSP instructions enabled.
* This is enabled by CP0 Status register MX(24) bit.
*/ */
static inline void check_dsp(DisasContext *ctx) static inline void check_dsp(DisasContext *ctx)
@ -2999,9 +3006,11 @@ static inline void check_dsp_r3(DisasContext *ctx)
} }
} }
/* This code generates a "reserved instruction" exception if the /*
CPU has corresponding flag set which indicates that the instruction * This code generates a "reserved instruction" exception if the
has been removed. */ * CPU has corresponding flag set which indicates that the instruction
* has been removed.
*/
static inline void check_insn_opc_removed(DisasContext *ctx, uint64_t flags) static inline void check_insn_opc_removed(DisasContext *ctx, uint64_t flags)
{ {
if (unlikely(ctx->insn_flags & flags)) { if (unlikely(ctx->insn_flags & flags)) {
@ -3024,8 +3033,10 @@ static inline void check_insn_opc_user_only(DisasContext *ctx, uint64_t flags)
#endif #endif
} }
/* This code generates a "reserved instruction" exception if the /*
CPU does not support the instruction set corresponding to flags. */ * This code generates a "reserved instruction" exception if the
* CPU does not support 64-bit paired-single (PS) floating point data type.
*/
static inline void check_insn(DisasContext *ctx, uint64_t flags) static inline void check_insn(DisasContext *ctx, uint64_t flags)
{ {
if (unlikely(!(ctx->insn_flags & flags))) { if (unlikely(!(ctx->insn_flags & flags))) {
@ -3033,8 +3044,10 @@ static inline void check_insn(DisasContext *ctx, uint64_t flags)
} }
} }
/* This code generates a "reserved instruction" exception if the /*
CPU does not support 64-bit paired-single (PS) floating point data type */ * This code generates a "reserved instruction" exception if the
* CPU does not support 64-bit paired-single (PS) floating point data type.
*/
static inline void check_ps(DisasContext *ctx) static inline void check_ps(DisasContext *ctx)
{ {
if (unlikely(!ctx->ps)) { if (unlikely(!ctx->ps)) {
@ -3044,8 +3057,10 @@ static inline void check_ps(DisasContext *ctx)
} }
#ifdef TARGET_MIPS64 #ifdef TARGET_MIPS64
/* This code generates a "reserved instruction" exception if 64-bit /*
instructions are not enabled. */ * This code generates a "reserved instruction" exception if 64-bit
* instructions are not enabled.
*/
static inline void check_mips_64(DisasContext *ctx) static inline void check_mips_64(DisasContext *ctx)
{ {
if (unlikely(!(ctx->hflags & MIPS_HFLAG_64))) { if (unlikely(!(ctx->hflags & MIPS_HFLAG_64))) {
@ -3158,10 +3173,12 @@ static inline void check_eva(DisasContext *ctx)
} }
/* Define small wrappers for gen_load_fpr* so that we have a uniform /*
calling interface for 32 and 64-bit FPRs. No sense in changing * Define small wrappers for gen_load_fpr* so that we have a uniform
all callers for gen_load_fpr32 when we need the CTX parameter for * calling interface for 32 and 64-bit FPRs. No sense in changing
this one use. */ * all callers for gen_load_fpr32 when we need the CTX parameter for
* this one use.
*/
#define gen_ldcmp_fpr32(ctx, x, y) gen_load_fpr32(ctx, x, y) #define gen_ldcmp_fpr32(ctx, x, y) gen_load_fpr32(ctx, x, y)
#define gen_ldcmp_fpr64(ctx, x, y) gen_load_fpr64(ctx, x, y) #define gen_ldcmp_fpr64(ctx, x, y) gen_load_fpr64(ctx, x, y)
#define FOP_CONDS(type, abs, fmt, ifmt, bits) \ #define FOP_CONDS(type, abs, fmt, ifmt, bits) \
@ -3413,9 +3430,11 @@ static void gen_ld(DisasContext *ctx, uint32_t opc,
int mem_idx = ctx->mem_idx; int mem_idx = ctx->mem_idx;
if (rt == 0 && ctx->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F)) { if (rt == 0 && ctx->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F)) {
/* Loongson CPU uses a load to zero register for prefetch. /*
We emulate it as a NOP. On other CPU we must perform the * Loongson CPU uses a load to zero register for prefetch.
actual memory access. */ * We emulate it as a NOP. On other CPU we must perform the
* actual memory access.
*/
return; return;
} }
@ -3441,8 +3460,10 @@ static void gen_ld(DisasContext *ctx, uint32_t opc,
break; break;
case OPC_LDL: case OPC_LDL:
t1 = tcg_temp_new(tcg_ctx); t1 = tcg_temp_new(tcg_ctx);
/* Do a byte access to possibly trigger a page /*
fault with the unaligned address. */ * Do a byte access to possibly trigger a page
* fault with the unaligned address.
*/
tcg_gen_qemu_ld_tl(ctx->uc, t1, t0, mem_idx, MO_UB); tcg_gen_qemu_ld_tl(ctx->uc, t1, t0, mem_idx, MO_UB);
tcg_gen_andi_tl(tcg_ctx, t1, t0, 7); tcg_gen_andi_tl(tcg_ctx, t1, t0, 7);
#ifndef TARGET_WORDS_BIGENDIAN #ifndef TARGET_WORDS_BIGENDIAN
@ -3463,8 +3484,10 @@ static void gen_ld(DisasContext *ctx, uint32_t opc,
break; break;
case OPC_LDR: case OPC_LDR:
t1 = tcg_temp_new(tcg_ctx); t1 = tcg_temp_new(tcg_ctx);
/* Do a byte access to possibly trigger a page /*
fault with the unaligned address. */ * Do a byte access to possibly trigger a page
* fault with the unaligned address.
*/
tcg_gen_qemu_ld_tl(ctx->uc, t1, t0, mem_idx, MO_UB); tcg_gen_qemu_ld_tl(ctx->uc, t1, t0, mem_idx, MO_UB);
tcg_gen_andi_tl(tcg_ctx, t1, t0, 7); tcg_gen_andi_tl(tcg_ctx, t1, t0, 7);
#ifdef TARGET_WORDS_BIGENDIAN #ifdef TARGET_WORDS_BIGENDIAN
@ -3568,8 +3591,10 @@ static void gen_ld(DisasContext *ctx, uint32_t opc,
/* fall through */ /* fall through */
case OPC_LWR: case OPC_LWR:
t1 = tcg_temp_new(tcg_ctx); t1 = tcg_temp_new(tcg_ctx);
/* Do a byte access to possibly trigger a page /*
fault with the unaligned address. */ * Do a byte access to possibly trigger a page
* fault with the unaligned address.
*/
tcg_gen_qemu_ld_tl(ctx->uc, t1, t0, mem_idx, MO_UB); tcg_gen_qemu_ld_tl(ctx->uc, t1, t0, mem_idx, MO_UB);
tcg_gen_andi_tl(tcg_ctx, t1, t0, 3); tcg_gen_andi_tl(tcg_ctx, t1, t0, 3);
#ifdef TARGET_WORDS_BIGENDIAN #ifdef TARGET_WORDS_BIGENDIAN
@ -3776,8 +3801,10 @@ static void gen_flt_ldst(DisasContext *ctx, uint32_t opc, int ft,
{ {
TCGContext *tcg_ctx = ctx->uc->tcg_ctx; TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
/* Don't do NOP if destination is zero: we must perform the actual /*
memory access. */ * Don't do NOP if destination is zero: we must perform the actual
* memory access.
*/
switch (opc) { switch (opc) {
case OPC_LWC1: case OPC_LWC1:
{ {
@ -3854,8 +3881,10 @@ static void gen_arith_imm(DisasContext *ctx, uint32_t opc,
target_ulong uimm = (target_long)imm; /* Sign extend to 32/64 bits */ target_ulong uimm = (target_long)imm; /* Sign extend to 32/64 bits */
if (rt == 0 && opc != OPC_ADDI && opc != OPC_DADDI) { if (rt == 0 && opc != OPC_ADDI && opc != OPC_DADDI) {
/* If no destination, treat it as a NOP. /*
For addi, we must generate the overflow exception when needed. */ * If no destination, treat it as a NOP.
* For addi, we must generate the overflow exception when needed.
*/
return; return;
} }
switch (opc) { switch (opc) {
@ -4090,8 +4119,10 @@ static void gen_arith(DisasContext *ctx, uint32_t opc,
if (rd == 0 && opc != OPC_ADD && opc != OPC_SUB if (rd == 0 && opc != OPC_ADD && opc != OPC_SUB
&& opc != OPC_DADD && opc != OPC_DSUB) { && opc != OPC_DADD && opc != OPC_DSUB) {
/* If no destination, treat it as a NOP. /*
For add & sub, we must generate the overflow exception when needed. */ * If no destination, treat it as a NOP.
* For add & sub, we must generate the overflow exception when needed.
*/
return; return;
} }
@ -4149,7 +4180,10 @@ static void gen_arith(DisasContext *ctx, uint32_t opc,
tcg_temp_free(tcg_ctx, t2); tcg_temp_free(tcg_ctx, t2);
tcg_gen_brcondi_tl(tcg_ctx, TCG_COND_GE, t1, 0, l1); tcg_gen_brcondi_tl(tcg_ctx, TCG_COND_GE, t1, 0, l1);
tcg_temp_free(tcg_ctx, t1); tcg_temp_free(tcg_ctx, t1);
/* operands of different sign, first operand and result different sign */ /*
* operands of different sign, first operand and the result
* of different sign
*/
generate_exception(ctx, EXCP_OVERFLOW); generate_exception(ctx, EXCP_OVERFLOW);
gen_set_label(tcg_ctx, l1); gen_set_label(tcg_ctx, l1);
gen_store_gpr(ctx, t0, rd); gen_store_gpr(ctx, t0, rd);
@ -4381,8 +4415,10 @@ static void gen_shift(DisasContext *ctx, uint32_t opc,
TCGv t0, t1; TCGv t0, t1;
if (rd == 0) { if (rd == 0) {
/* If no destination, treat it as a NOP. /*
For add & sub, we must generate the overflow exception when needed. */ * If no destination, treat it as a NOP.
* For add & sub, we must generate the overflow exception when needed.
*/
return; return;
} }
@ -5701,8 +5737,10 @@ static void gen_loongson_multimedia(DisasContext *ctx, int rd, int rs, int rt)
break; break;
case OPC_SRA_CP2: case OPC_SRA_CP2:
case OPC_DSRA_CP2: case OPC_DSRA_CP2:
/* Since SRA is UndefinedResult without sign-extended inputs, /*
we can treat SRA and DSRA the same. */ * Since SRA is UndefinedResult without sign-extended inputs,
* we can treat SRA and DSRA the same.
*/
tcg_gen_sar_i64(tcg_ctx, t0, t0, t1); tcg_gen_sar_i64(tcg_ctx, t0, t0, t1);
break; break;
case OPC_SRL_CP2: case OPC_SRL_CP2:
@ -5778,8 +5816,10 @@ static void gen_loongson_multimedia(DisasContext *ctx, int rd, int rs, int rt)
case OPC_SLT_CP2: case OPC_SLT_CP2:
case OPC_SLEU_CP2: case OPC_SLEU_CP2:
case OPC_SLE_CP2: case OPC_SLE_CP2:
/* ??? Document is unclear: Set FCC[CC]. Does that mean the /*
FD field is the CC field? */ * ??? Document is unclear: Set FCC[CC]. Does that mean the
* FD field is the CC field?
*/
default: default:
MIPS_INVAL("loongson_cp2"); MIPS_INVAL("loongson_cp2");
generate_exception_end(ctx, EXCP_RI); generate_exception_end(ctx, EXCP_RI);
@ -5998,8 +6038,10 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc,
case OPC_JALR: case OPC_JALR:
/* Jump to register */ /* Jump to register */
if (offset != 0 && offset != 16) { if (offset != 0 && offset != 16) {
/* Hint = 0 is JR/JALR, hint 16 is JR.HB/JALR.HB, the /*
others are reserved. */ * Hint = 0 is JR/JALR, hint 16 is JR.HB/JALR.HB, the
* others are reserved.
*/
MIPS_INVAL("jump hint"); MIPS_INVAL("jump hint");
generate_exception_end(ctx, EXCP_RI); generate_exception_end(ctx, EXCP_RI);
goto out; goto out;
@ -6035,8 +6077,10 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc,
/* Treat as NOP. */ /* Treat as NOP. */
goto out; goto out;
case OPC_BLTZAL: /* 0 < 0 */ case OPC_BLTZAL: /* 0 < 0 */
/* Handle as an unconditional branch to get correct delay /*
slot checking. */ * Handle as an unconditional branch to get correct delay
* slot checking.
*/
blink = 31; blink = 31;
btgt = ctx->base.pc_next + insn_bytes + delayslot_size; btgt = ctx->base.pc_next + insn_bytes + delayslot_size;
ctx->hflags |= MIPS_HFLAG_B; ctx->hflags |= MIPS_HFLAG_B;
@ -6215,8 +6259,10 @@ static void gen_compute_branch_nm(DisasContext *ctx, uint32_t opc,
case OPC_JALR: case OPC_JALR:
/* Jump to register */ /* Jump to register */
if (offset != 0 && offset != 16) { if (offset != 0 && offset != 16) {
/* Hint = 0 is JR/JALR, hint 16 is JR.HB/JALR.HB, the /*
others are reserved. */ * Hint = 0 is JR/JALR, hint 16 is JR.HB/JALR.HB, the
* others are reserved.
*/
MIPS_INVAL("jump hint"); MIPS_INVAL("jump hint");
generate_exception_end(ctx, EXCP_RI); generate_exception_end(ctx, EXCP_RI);
goto out; goto out;
@ -6314,8 +6360,10 @@ static void gen_bitops(DisasContext *ctx, uint32_t opc, int rt,
if (msb != 31) { if (msb != 31) {
tcg_gen_extract_tl(tcg_ctx, t0, t1, lsb, msb + 1); tcg_gen_extract_tl(tcg_ctx, t0, t1, lsb, msb + 1);
} else { } else {
/* The two checks together imply that lsb == 0, /*
so this is a simple sign-extension. */ * The two checks together imply that lsb == 0,
* so this is a simple sign-extension.
*/
tcg_gen_ext32s_tl(tcg_ctx, t0, t1); tcg_gen_ext32s_tl(tcg_ctx, t0, t1);
} }
break; break;
@ -6782,10 +6830,12 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case CP0_REGISTER_17: case CP0_REGISTER_17:
switch (sel) { switch (sel) {
case 0: case 0:
/* LLAddr is read-only (the only exception is bit 0 if LLB is /*
supported); the CP0_LLAddr_rw_bitmask does not seem to be * LLAddr is read-only (the only exception is bit 0 if LLB is
relevant for modern MIPS cores supporting MTHC0, therefore * supported); the CP0_LLAddr_rw_bitmask does not seem to be
treating MTHC0 to LLAddr as NOP. */ * relevant for modern MIPS cores supporting MTHC0, therefore
* treating MTHC0 to LLAddr as NOP.
*/
register_name = "LLAddr"; register_name = "LLAddr";
break; break;
case 1: case 1:
@ -7010,7 +7060,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
register_name = "Context"; register_name = "Context";
break; break;
case 1: case 1:
// gen_helper_mfc0_contextconfig(arg); /* SmartMIPS ASE */ /* gen_helper_mfc0_contextconfig(arg); - SmartMIPS ASE */
register_name = "ContextConfig"; register_name = "ContextConfig";
goto cp0_unimplemented; goto cp0_unimplemented;
case 2: case 2:
@ -7154,9 +7204,11 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
//if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { //if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
// gen_io_end(); // gen_io_end();
//} //}
/* Break the TB to be able to take timer interrupts immediately /*
after reading count. DISAS_STOP isn't sufficient, we need to * Break the TB to be able to take timer interrupts immediately
ensure we break completely out of translated code. */ * after reading count. DISAS_STOP isn't sufficient, we need to
* ensure we break completely out of translated code.
*/
gen_save_pc(ctx, ctx->base.pc_next + 4); gen_save_pc(ctx, ctx->base.pc_next + 4);
ctx->base.is_jmp = DISAS_EXIT; ctx->base.is_jmp = DISAS_EXIT;
register_name = "Count"; register_name = "Count";
@ -7436,31 +7488,31 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
register_name = "Performance0"; register_name = "Performance0";
break; break;
case 1: case 1:
// gen_helper_mfc0_performance1(arg); /* gen_helper_mfc0_performance1(arg); */
register_name = "Performance1"; register_name = "Performance1";
goto cp0_unimplemented; goto cp0_unimplemented;
case 2: case 2:
// gen_helper_mfc0_performance2(arg); /* gen_helper_mfc0_performance2(arg); */
register_name = "Performance2"; register_name = "Performance2";
goto cp0_unimplemented; goto cp0_unimplemented;
case 3: case 3:
// gen_helper_mfc0_performance3(arg); /* gen_helper_mfc0_performance3(arg); */
register_name = "Performance3"; register_name = "Performance3";
goto cp0_unimplemented; goto cp0_unimplemented;
case 4: case 4:
// gen_helper_mfc0_performance4(arg); /* gen_helper_mfc0_performance4(arg); */
register_name = "Performance4"; register_name = "Performance4";
goto cp0_unimplemented; goto cp0_unimplemented;
case 5: case 5:
// gen_helper_mfc0_performance5(arg); /* gen_helper_mfc0_performance5(arg); */
register_name = "Performance5"; register_name = "Performance5";
goto cp0_unimplemented; goto cp0_unimplemented;
case 6: case 6:
// gen_helper_mfc0_performance6(arg); /* gen_helper_mfc0_performance6(arg); */
register_name = "Performance6"; register_name = "Performance6";
goto cp0_unimplemented; goto cp0_unimplemented;
case 7: case 7:
// gen_helper_mfc0_performance7(arg); /* gen_helper_mfc0_performance7(arg); */
register_name = "Performance7"; register_name = "Performance7";
goto cp0_unimplemented; goto cp0_unimplemented;
default: default:
@ -7949,9 +8001,11 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case 0: case 0:
save_cpu_state(ctx, 1); save_cpu_state(ctx, 1);
gen_helper_mtc0_cause(tcg_ctx, tcg_ctx->cpu_env, arg); gen_helper_mtc0_cause(tcg_ctx, tcg_ctx->cpu_env, arg);
/* Stop translation as we may have triggered an interrupt. /*
* Stop translation as we may have triggered an interrupt.
* DISAS_STOP isn't sufficient, we need to ensure we break out of * DISAS_STOP isn't sufficient, we need to ensure we break out of
* translated code to check for pending interrupts. */ * translated code to check for pending interrupts.
*/
gen_save_pc(ctx, ctx->base.pc_next + 4); gen_save_pc(ctx, ctx->base.pc_next + 4);
ctx->base.is_jmp = DISAS_EXIT; ctx->base.is_jmp = DISAS_EXIT;
register_name = "Cause"; register_name = "Cause";
@ -8176,31 +8230,31 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
register_name = "Performance0"; register_name = "Performance0";
break; break;
case 1: case 1:
// gen_helper_mtc0_performance1(arg); /* gen_helper_mtc0_performance1(arg); */
register_name = "Performance1"; register_name = "Performance1";
goto cp0_unimplemented; goto cp0_unimplemented;
case 2: case 2:
// gen_helper_mtc0_performance2(arg); /* gen_helper_mtc0_performance2(arg); */
register_name = "Performance2"; register_name = "Performance2";
goto cp0_unimplemented; goto cp0_unimplemented;
case 3: case 3:
// gen_helper_mtc0_performance3(arg); /* gen_helper_mtc0_performance3(arg); */
register_name = "Performance3"; register_name = "Performance3";
goto cp0_unimplemented; goto cp0_unimplemented;
case 4: case 4:
// gen_helper_mtc0_performance4(arg); /* gen_helper_mtc0_performance4(arg); */
register_name = "Performance4"; register_name = "Performance4";
goto cp0_unimplemented; goto cp0_unimplemented;
case 5: case 5:
// gen_helper_mtc0_performance5(arg); /* gen_helper_mtc0_performance5(arg); */
register_name = "Performance5"; register_name = "Performance5";
goto cp0_unimplemented; goto cp0_unimplemented;
case 6: case 6:
// gen_helper_mtc0_performance6(arg); /* gen_helper_mtc0_performance6(arg); */
register_name = "Performance6"; register_name = "Performance6";
goto cp0_unimplemented; goto cp0_unimplemented;
case 7: case 7:
// gen_helper_mtc0_performance7(arg); /* gen_helper_mtc0_performance7(arg); */
register_name = "Performance7"; register_name = "Performance7";
goto cp0_unimplemented; goto cp0_unimplemented;
default: default:
@ -8617,9 +8671,11 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
//if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { //if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
// gen_io_end(); // gen_io_end();
//} //}
/* Break the TB to be able to take timer interrupts immediately /*
after reading count. DISAS_STOP isn't sufficient, we need to * Break the TB to be able to take timer interrupts immediately
ensure we break completely out of translated code. */ * after reading count. DISAS_STOP isn't sufficient, we need to
* ensure we break completely out of translated code.
*/
gen_save_pc(ctx, ctx->base.pc_next + 4); gen_save_pc(ctx, ctx->base.pc_next + 4);
ctx->base.is_jmp = DISAS_EXIT; ctx->base.is_jmp = DISAS_EXIT;
register_name = "Count"; register_name = "Count";
@ -8891,31 +8947,31 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
register_name = "Performance0"; register_name = "Performance0";
break; break;
case 1: case 1:
// gen_helper_dmfc0_performance1(arg); /* gen_helper_dmfc0_performance1(arg); */
register_name = "Performance1"; register_name = "Performance1";
goto cp0_unimplemented; goto cp0_unimplemented;
case 2: case 2:
// gen_helper_dmfc0_performance2(arg); /* gen_helper_dmfc0_performance2(arg); */
register_name = "Performance2"; register_name = "Performance2";
goto cp0_unimplemented; goto cp0_unimplemented;
case 3: case 3:
// gen_helper_dmfc0_performance3(arg); /* gen_helper_dmfc0_performance3(arg); */
register_name = "Performance3"; register_name = "Performance3";
goto cp0_unimplemented; goto cp0_unimplemented;
case 4: case 4:
// gen_helper_dmfc0_performance4(arg); /* gen_helper_dmfc0_performance4(arg); */
register_name = "Performance4"; register_name = "Performance4";
goto cp0_unimplemented; goto cp0_unimplemented;
case 5: case 5:
// gen_helper_dmfc0_performance5(arg); /* gen_helper_dmfc0_performance5(arg); */
register_name = "Performance5"; register_name = "Performance5";
goto cp0_unimplemented; goto cp0_unimplemented;
case 6: case 6:
// gen_helper_dmfc0_performance6(arg); /* gen_helper_dmfc0_performance6(arg); */
register_name = "Performance6"; register_name = "Performance6";
goto cp0_unimplemented; goto cp0_unimplemented;
case 7: case 7:
// gen_helper_dmfc0_performance7(arg); /* gen_helper_dmfc0_performance7(arg); */
register_name = "Performance7"; register_name = "Performance7";
goto cp0_unimplemented; goto cp0_unimplemented;
default: default:
@ -9399,9 +9455,11 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case 0: case 0:
save_cpu_state(ctx, 1); save_cpu_state(ctx, 1);
gen_helper_mtc0_cause(tcg_ctx, tcg_ctx->cpu_env, arg); gen_helper_mtc0_cause(tcg_ctx, tcg_ctx->cpu_env, arg);
/* Stop translation as we may have triggered an interrupt. /*
* Stop translation as we may have triggered an interrupt.
* DISAS_STOP isn't sufficient, we need to ensure we break out of * DISAS_STOP isn't sufficient, we need to ensure we break out of
* translated code to check for pending interrupts. */ * translated code to check for pending interrupts.
*/
gen_save_pc(ctx, ctx->base.pc_next + 4); gen_save_pc(ctx, ctx->base.pc_next + 4);
ctx->base.is_jmp = DISAS_EXIT; ctx->base.is_jmp = DISAS_EXIT;
register_name = "Cause"; register_name = "Cause";
@ -9613,31 +9671,31 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
register_name = "Performance0"; register_name = "Performance0";
break; break;
case 1: case 1:
// gen_helper_mtc0_performance1(tcg_ctx->cpu_env, arg); /* gen_helper_mtc0_performance1(tcg_ctx->cpu_env, arg); */
register_name = "Performance1"; register_name = "Performance1";
goto cp0_unimplemented; goto cp0_unimplemented;
case 2: case 2:
// gen_helper_mtc0_performance2(tcg_ctx->cpu_env, arg); /* gen_helper_mtc0_performance2(tcg_ctx->cpu_env, arg); */
register_name = "Performance2"; register_name = "Performance2";
goto cp0_unimplemented; goto cp0_unimplemented;
case 3: case 3:
// gen_helper_mtc0_performance3(tcg_ctx->cpu_env, arg); /* gen_helper_mtc0_performance3(tcg_ctx->cpu_env, arg); */
register_name = "Performance3"; register_name = "Performance3";
goto cp0_unimplemented; goto cp0_unimplemented;
case 4: case 4:
// gen_helper_mtc0_performance4(tcg_ctx->cpu_env, arg); /* gen_helper_mtc0_performance4(tcg_ctx->cpu_env, arg); */
register_name = "Performance4"; register_name = "Performance4";
goto cp0_unimplemented; goto cp0_unimplemented;
case 5: case 5:
// gen_helper_mtc0_performance5(tcg_ctx->cpu_env, arg); /* gen_helper_mtc0_performance5(tcg_ctx->cpu_env, arg); */
register_name = "Performance5"; register_name = "Performance5";
goto cp0_unimplemented; goto cp0_unimplemented;
case 6: case 6:
// gen_helper_mtc0_performance6(tcg_ctx->cpu_env, arg); /* gen_helper_mtc0_performance6(tcg_ctx->cpu_env, arg); */
register_name = "Performance6"; register_name = "Performance6";
goto cp0_unimplemented; goto cp0_unimplemented;
case 7: case 7:
// gen_helper_mtc0_performance7(tcg_ctx->cpu_env, arg); /* gen_helper_mtc0_performance7(tcg_ctx->cpu_env, arg); */
register_name = "Performance7"; register_name = "Performance7";
goto cp0_unimplemented; goto cp0_unimplemented;
default: default:
@ -9997,10 +10055,12 @@ static void gen_mttr(CPUMIPSState *env, DisasContext *ctx, int rd, int rt,
if ((env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) == 0 && if ((env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) == 0 &&
((env->tcs[other_tc].CP0_TCBind & (0xf << CP0TCBd_CurVPE)) != ((env->tcs[other_tc].CP0_TCBind & (0xf << CP0TCBd_CurVPE)) !=
(env->active_tc.CP0_TCBind & (0xf << CP0TCBd_CurVPE)))) { (env->active_tc.CP0_TCBind & (0xf << CP0TCBd_CurVPE)))) {
/* NOP */ ; /* NOP */
;
} else if ((env->CP0_VPEControl & (0xff << CP0VPECo_TargTC)) > } else if ((env->CP0_VPEControl & (0xff << CP0VPECo_TargTC)) >
(env->mvp->CP0_MVPConf0 & (0xff << CP0MVPC0_PTC))) { (env->mvp->CP0_MVPConf0 & (0xff << CP0MVPC0_PTC))) {
/* NOP */ ; /* NOP */
;
} else if (u == 0) { } else if (u == 0) {
switch (rd) { switch (rd) {
case 1: case 1:
@ -12470,8 +12530,10 @@ static void gen_flt3_ldst(DisasContext *ctx, uint32_t opc,
} else { } else {
gen_op_addr_add(ctx, t0, cpu_gpr[base], cpu_gpr[index]); gen_op_addr_add(ctx, t0, cpu_gpr[base], cpu_gpr[index]);
} }
/* Don't do NOP if destination is zero: we must perform the actual /*
memory access. */ * Don't do NOP if destination is zero: we must perform the actual
* memory access.
*/
switch (opc) { switch (opc) {
case OPC_LWXC1: case OPC_LWXC1:
check_cop1x(ctx); check_cop1x(ctx);
@ -12802,8 +12864,10 @@ static void gen_rdhwr(DisasContext *ctx, int rt, int rd, int sel)
TCGv t0; TCGv t0;
#if !defined(CONFIG_USER_ONLY) #if !defined(CONFIG_USER_ONLY)
/* The Linux kernel will emulate rdhwr if it's not supported natively. /*
Therefore only check the ISA in system mode. */ * The Linux kernel will emulate rdhwr if it's not supported natively.
* Therefore only check the ISA in system mode.
*/
check_insn(ctx, ISA_MIPS32R2); check_insn(ctx, ISA_MIPS32R2);
#endif #endif
t0 = tcg_temp_new(tcg_ctx); t0 = tcg_temp_new(tcg_ctx);
@ -12831,9 +12895,11 @@ static void gen_rdhwr(DisasContext *ctx, int rt, int rd, int sel)
} }
#endif #endif
gen_store_gpr(ctx, t0, rt); gen_store_gpr(ctx, t0, rt);
/* Break the TB to be able to take timer interrupts immediately /*
after reading count. DISAS_STOP isn't sufficient, we need to ensure * Break the TB to be able to take timer interrupts immediately
we break completely out of translated code. */ * after reading count. DISAS_STOP isn't sufficient, we need to ensure
* we break completely out of translated code.
*/
gen_save_pc(ctx, ctx->base.pc_next + 4); gen_save_pc(ctx, ctx->base.pc_next + 4);
ctx->base.is_jmp = DISAS_EXIT; ctx->base.is_jmp = DISAS_EXIT;
break; break;
@ -12844,7 +12910,8 @@ static void gen_rdhwr(DisasContext *ctx, int rt, int rd, int sel)
case 4: case 4:
check_insn(ctx, ISA_MIPS32R6); check_insn(ctx, ISA_MIPS32R6);
if (sel != 0) { if (sel != 0) {
/* Performance counter registers are not implemented other than /*
* Performance counter registers are not implemented other than
* control register 0. * control register 0.
*/ */
generate_exception(ctx, EXCP_RI); generate_exception(ctx, EXCP_RI);
@ -12889,8 +12956,10 @@ static inline void clear_branch_hflags(DisasContext *ctx)
if (ctx->base.is_jmp == DISAS_NEXT) { if (ctx->base.is_jmp == DISAS_NEXT) {
save_cpu_state(ctx, 0); save_cpu_state(ctx, 0);
} else { } else {
/* it is not safe to save ctx->hflags as hflags may be changed /*
in execution time by the instruction in delay / forbidden slot. */ * it is not safe to save ctx->hflags as hflags may be changed
* in execution time by the instruction in delay / forbidden slot.
*/
tcg_gen_andi_i32(tcg_ctx, tcg_ctx->hflags, tcg_ctx->hflags, ~MIPS_HFLAG_BMASK); tcg_gen_andi_i32(tcg_ctx, tcg_ctx->hflags, tcg_ctx->hflags, ~MIPS_HFLAG_BMASK);
} }
} }
@ -13700,8 +13769,10 @@ static int decode_extended_mips16_opc(CPUMIPSState *env, DisasContext *ctx)
| ((ctx->opcode >> 21) & 0x3f) << 5 | ((ctx->opcode >> 21) & 0x3f) << 5
| (ctx->opcode & 0x1f)); | (ctx->opcode & 0x1f));
/* The extended opcodes cleverly reuse the opcodes from their 16-bit /*
counterparts. */ * The extended opcodes cleverly reuse the opcodes from their 16-bit
* counterparts.
*/
switch (op) { switch (op) {
case M16_OPC_ADDIUSP: case M16_OPC_ADDIUSP:
gen_arith_imm(ctx, OPC_ADDIU, rx, 29, imm); gen_arith_imm(ctx, OPC_ADDIU, rx, 29, imm);
@ -14190,7 +14261,8 @@ static int decode_mips16_opc(CPUMIPSState *env, DisasContext *ctx, bool *insn_ne
} }
break; break;
case RR_SDBBP: case RR_SDBBP:
/* XXX: not clear which exception should be raised /*
* XXX: not clear which exception should be raised
* when in debug mode... * when in debug mode...
*/ */
check_insn(ctx, ISA_MIPS32); check_insn(ctx, ISA_MIPS32);
@ -14497,8 +14569,10 @@ enum {
/* POOL32A encoding of minor opcode field */ /* POOL32A encoding of minor opcode field */
enum { enum {
/* These opcodes are distinguished only by bits 9..6; those bits are /*
* what are recorded below. */ * These opcodes are distinguished only by bits 9..6; those bits are
* what are recorded below.
*/
SLL32 = 0x0, SLL32 = 0x0,
SRL32 = 0x1, SRL32 = 0x1,
SRA = 0x2, SRA = 0x2,
@ -15147,8 +15221,10 @@ static void gen_pool16c_insn(DisasContext *ctx)
{ {
int reg = ctx->opcode & 0x1f; int reg = ctx->opcode & 0x1f;
gen_compute_branch(ctx, OPC_JR, 2, reg, 0, 0, 0); gen_compute_branch(ctx, OPC_JR, 2, reg, 0, 0, 0);
/* Let normal delay slot handling in our caller take us /*
to the branch target. */ * Let normal delay slot handling in our caller take us
* to the branch target.
*/
} }
break; break;
case JALR16 + 0: case JALR16 + 0:
@ -15173,7 +15249,8 @@ static void gen_pool16c_insn(DisasContext *ctx)
generate_exception_end(ctx, EXCP_BREAK); generate_exception_end(ctx, EXCP_BREAK);
break; break;
case SDBBP16: case SDBBP16:
/* XXX: not clear which exception should be raised /*
* XXX: not clear which exception should be raised
* when in debug mode... * when in debug mode...
*/ */
check_insn(ctx, ISA_MIPS32); check_insn(ctx, ISA_MIPS32);
@ -15185,8 +15262,10 @@ static void gen_pool16c_insn(DisasContext *ctx)
int imm = ZIMM(ctx->opcode, 0, 5); int imm = ZIMM(ctx->opcode, 0, 5);
gen_compute_branch(ctx, OPC_JR, 2, 31, 0, 0, 0); gen_compute_branch(ctx, OPC_JR, 2, 31, 0, 0, 0);
gen_arith_imm(ctx, OPC_ADDIU, 29, 29, imm << 2); gen_arith_imm(ctx, OPC_ADDIU, 29, 29, imm << 2);
/* Let normal delay slot handling in our caller take us /*
to the branch target. */ * Let normal delay slot handling in our caller take us
* to the branch target.
*/
} }
break; break;
default: default:
@ -15690,8 +15769,10 @@ static void gen_pool32axf(CPUMIPSState *env, DisasContext *ctx, int rt, int rs)
save_cpu_state(ctx, 1); save_cpu_state(ctx, 1);
gen_helper_ei(tcg_ctx, t0, tcg_ctx->cpu_env); gen_helper_ei(tcg_ctx, t0, tcg_ctx->cpu_env);
gen_store_gpr(ctx, t0, rs); gen_store_gpr(ctx, t0, rs);
/* DISAS_STOP isn't sufficient, we need to ensure we break out /*
of translated code to check for pending interrupts. */ * DISAS_STOP isn't sufficient, we need to ensure we break out
* of translated code to check for pending interrupts.
*/
gen_save_pc(ctx, ctx->base.pc_next + 4); gen_save_pc(ctx, ctx->base.pc_next + 4);
ctx->base.is_jmp = DISAS_EXIT; ctx->base.is_jmp = DISAS_EXIT;
tcg_temp_free(tcg_ctx, t0); tcg_temp_free(tcg_ctx, t0);
@ -15767,9 +15848,10 @@ static void gen_pool32axf(CPUMIPSState *env, DisasContext *ctx, int rt, int rs)
} }
} }
/* Values for microMIPS fmt field. Variable-width, depending on which /*
formats the instruction supports. */ * Values for microMIPS fmt field. Variable-width, depending on which
* formats the instruction supports.
*/
enum { enum {
FMT_SD_S = 0, FMT_SD_S = 0,
FMT_SD_D = 1, FMT_SD_D = 1,
@ -16842,8 +16924,10 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
case TNEI: /* SYNCI */ case TNEI: /* SYNCI */
if (ctx->insn_flags & ISA_MIPS32R6) { if (ctx->insn_flags & ISA_MIPS32R6) {
/* SYNCI */ /* SYNCI */
/* Break the TB to be able to sync copied instructions /*
immediately */ * Break the TB to be able to sync copied instructions
* immediately
*/
ctx->base.is_jmp = DISAS_STOP; ctx->base.is_jmp = DISAS_STOP;
} else { } else {
/* TNEI */ /* TNEI */
@ -16863,9 +16947,11 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
check_insn_opc_removed(ctx, ISA_MIPS32R6); check_insn_opc_removed(ctx, ISA_MIPS32R6);
gen_compute_branch(ctx, minor == BNEZC ? OPC_BNE : OPC_BEQ, gen_compute_branch(ctx, minor == BNEZC ? OPC_BNE : OPC_BEQ,
4, rs, 0, imm << 1, 0); 4, rs, 0, imm << 1, 0);
/* Compact branches don't have a delay slot, so just let /*
the normal delay slot handling take us to the branch * Compact branches don't have a delay slot, so just let
target. */ * the normal delay slot handling take us to the branch
* target.
*/
break; break;
case LUI: case LUI:
check_insn_opc_removed(ctx, ISA_MIPS32R6); check_insn_opc_removed(ctx, ISA_MIPS32R6);
@ -16873,8 +16959,10 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
break; break;
case SYNCI: case SYNCI:
check_insn_opc_removed(ctx, ISA_MIPS32R6); check_insn_opc_removed(ctx, ISA_MIPS32R6);
/* Break the TB to be able to sync copied instructions /*
immediately */ * Break the TB to be able to sync copied instructions
* immediately
*/
ctx->base.is_jmp = DISAS_STOP; ctx->base.is_jmp = DISAS_STOP;
break; break;
case BC2F: case BC2F:
@ -17459,7 +17547,8 @@ static int decode_micromips_opc(CPUMIPSState *env, DisasContext *ctx, bool *insn
break; break;
} }
if (ctx->insn_flags & ISA_MIPS32R6) { if (ctx->insn_flags & ISA_MIPS32R6) {
/* In the Release 6 the register number location in /*
* In the Release 6 the register number location in
* the instruction encoding has changed. * the instruction encoding has changed.
*/ */
gen_arith(ctx, opc, rs1, rd, rs2); gen_arith(ctx, opc, rs1, rd, rs2);
@ -21204,9 +21293,11 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
gen_p_lsx(ctx, rd, rs, rt); gen_p_lsx(ctx, rd, rs, rt);
break; break;
case NM_LSA: case NM_LSA:
/* In nanoMIPS, the shift field directly encodes the shift /*
* In nanoMIPS, the shift field directly encodes the shift
* amount, meaning that the supported shift values are in * amount, meaning that the supported shift values are in
* the range 0 to 3 (instead of 1 to 4 in MIPSR6). */ * the range 0 to 3 (instead of 1 to 4 in MIPSR6).
*/
gen_lsa(ctx, OPC_LSA, rd, rs, rt, gen_lsa(ctx, OPC_LSA, rd, rs, rt,
extract32(ctx->opcode, 9, 2) - 1); extract32(ctx->opcode, 9, 2) - 1);
break; break;
@ -21561,8 +21652,10 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
case NM_P_PREFU12: case NM_P_PREFU12:
if (rt == 31) { if (rt == 31) {
/* SYNCI */ /* SYNCI */
/* Break the TB to be able to sync copied instructions /*
immediately */ * Break the TB to be able to sync copied instructions
* immediately
*/
ctx->base.is_jmp = DISAS_STOP; ctx->base.is_jmp = DISAS_STOP;
} else { } else {
/* PREF */ /* PREF */
@ -21658,8 +21751,10 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
case NM_P_PREFS9: case NM_P_PREFS9:
if (rt == 31) { if (rt == 31) {
/* SYNCI */ /* SYNCI */
/* Break the TB to be able to sync copied instructions /*
immediately */ * Break the TB to be able to sync copied instructions
* immediately
*/
ctx->base.is_jmp = DISAS_STOP; ctx->base.is_jmp = DISAS_STOP;
} else { } else {
/* PREF */ /* PREF */
@ -21751,8 +21846,10 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
/* case NM_SYNCIE */ /* case NM_SYNCIE */
check_eva(ctx); check_eva(ctx);
check_cp0_enabled(ctx); check_cp0_enabled(ctx);
/* Break the TB to be able to sync copied instructions /*
immediately */ * Break the TB to be able to sync copied instructions
* immediately
*/
ctx->base.is_jmp = DISAS_STOP; ctx->base.is_jmp = DISAS_STOP;
} else { } else {
/* case NM_PREFE */ /* case NM_PREFE */
@ -23151,8 +23248,10 @@ static void gen_mipsdsp_multiply(DisasContext *ctx, uint32_t op1, uint32_t op2,
gen_load_gpr(ctx, v2_t, v2); gen_load_gpr(ctx, v2_t, v2);
switch (op1) { switch (op1) {
/* OPC_MULT_G_2E, OPC_ADDUH_QB_DSP, OPC_MUL_PH_DSP have /*
* the same mask and op1. */ * OPC_MULT_G_2E, OPC_ADDUH_QB_DSP, OPC_MUL_PH_DSP have
* the same mask and op1.
*/
case OPC_MULT_G_2E: case OPC_MULT_G_2E:
check_dsp_r2(ctx); check_dsp_r2(ctx);
switch (op2) { switch (op2) {
@ -24129,8 +24228,10 @@ static void decode_opc_special_r6(CPUMIPSState *env, DisasContext *ctx)
case R6_OPC_CLO: case R6_OPC_CLO:
case R6_OPC_CLZ: case R6_OPC_CLZ:
if (rt == 0 && sa == 1) { if (rt == 0 && sa == 1) {
/* Major opcode and function field is shared with preR6 MFHI/MTHI. /*
We need additionally to check other fields */ * Major opcode and function field is shared with preR6 MFHI/MTHI.
* We need additionally to check other fields.
*/
gen_cl(ctx, op1, rd, rs); gen_cl(ctx, op1, rd, rs);
} else { } else {
generate_exception_end(ctx, EXCP_RI); generate_exception_end(ctx, EXCP_RI);
@ -24151,8 +24252,10 @@ static void decode_opc_special_r6(CPUMIPSState *env, DisasContext *ctx)
case R6_OPC_DCLO: case R6_OPC_DCLO:
case R6_OPC_DCLZ: case R6_OPC_DCLZ:
if (rt == 0 && sa == 1) { if (rt == 0 && sa == 1) {
/* Major opcode and function field is shared with preR6 MFHI/MTHI. /*
We need additionally to check other fields */ * Major opcode and function field is shared with preR6 MFHI/MTHI.
* We need additionally to check other fields.
*/
check_mips_64(ctx); check_mips_64(ctx);
gen_cl(ctx, op1, rd, rs); gen_cl(ctx, op1, rd, rs);
} else { } else {
@ -27124,8 +27227,10 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx)
case OPC_MODU_G_2E: case OPC_MODU_G_2E:
case OPC_MULT_G_2E: case OPC_MULT_G_2E:
case OPC_MULTU_G_2E: case OPC_MULTU_G_2E:
/* OPC_MULT_G_2E, OPC_ADDUH_QB_DSP, OPC_MUL_PH_DSP have /*
* the same mask and op1. */ * OPC_MULT_G_2E, OPC_ADDUH_QB_DSP, OPC_MUL_PH_DSP have
* the same mask and op1.
*/
if ((ctx->insn_flags & ASE_DSP_R2) && (op1 == OPC_MULT_G_2E)) { if ((ctx->insn_flags & ASE_DSP_R2) && (op1 == OPC_MULT_G_2E)) {
op2 = MASK_ADDUH_QB(ctx->opcode); op2 = MASK_ADDUH_QB(ctx->opcode);
switch (op2) { switch (op2) {
@ -29344,8 +29449,10 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx, bool *insn_need_pat
break; break;
case OPC_SYNCI: case OPC_SYNCI:
check_insn(ctx, ISA_MIPS32R2); check_insn(ctx, ISA_MIPS32R2);
/* Break the TB to be able to sync copied instructions /*
immediately */ * Break the TB to be able to sync copied instructions
* immediately
*/
ctx->base.is_jmp = DISAS_STOP; ctx->base.is_jmp = DISAS_STOP;
break; break;
case OPC_BPOSGE32: /* MIPS DSP branch */ case OPC_BPOSGE32: /* MIPS DSP branch */
@ -29462,8 +29569,10 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx, bool *insn_need_pat
save_cpu_state(ctx, 1); save_cpu_state(ctx, 1);
gen_helper_di(tcg_ctx, t0, tcg_ctx->cpu_env); gen_helper_di(tcg_ctx, t0, tcg_ctx->cpu_env);
gen_store_gpr(ctx, t0, rt); gen_store_gpr(ctx, t0, rt);
/* Stop translation as we may have switched /*
the execution mode. */ * Stop translation as we may have switched
* the execution mode.
*/
ctx->base.is_jmp = DISAS_STOP; ctx->base.is_jmp = DISAS_STOP;
break; break;
case OPC_EI: case OPC_EI:
@ -29471,8 +29580,10 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx, bool *insn_need_pat
save_cpu_state(ctx, 1); save_cpu_state(ctx, 1);
gen_helper_ei(tcg_ctx, t0, tcg_ctx->cpu_env); gen_helper_ei(tcg_ctx, t0, tcg_ctx->cpu_env);
gen_store_gpr(ctx, t0, rt); gen_store_gpr(ctx, t0, rt);
/* DISAS_STOP isn't sufficient, we need to ensure we break /*
out of translated code to check for pending interrupts */ * DISAS_STOP isn't sufficient, we need to ensure we break
* out of translated code to check for pending interrupts
*/
gen_save_pc(ctx, ctx->base.pc_next + 4); gen_save_pc(ctx, ctx->base.pc_next + 4);
ctx->base.is_jmp = DISAS_EXIT; ctx->base.is_jmp = DISAS_EXIT;
break; break;
@ -30057,10 +30168,12 @@ static bool mips_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs,
save_cpu_state(ctx, 1); save_cpu_state(ctx, 1);
ctx->base.is_jmp = DISAS_NORETURN; ctx->base.is_jmp = DISAS_NORETURN;
gen_helper_raise_exception_debug(tcg_ctx, tcg_ctx->cpu_env); gen_helper_raise_exception_debug(tcg_ctx, tcg_ctx->cpu_env);
/* The address covered by the breakpoint must be included in /*
[tb->pc, tb->pc + tb->size) in order to for it to be * The address covered by the breakpoint must be included in
properly cleared -- thus we increment the PC here so that * [tb->pc, tb->pc + tb->size) in order to for it to be
the logic setting tb->size below does the right thing. */ * properly cleared -- thus we increment the PC here so that
* the logic setting tb->size below does the right thing.
*/
ctx->base.pc_next += 4; ctx->base.pc_next += 4;
return true; return true;
} }
@ -30106,14 +30219,18 @@ static void mips_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
if (ctx->hflags & MIPS_HFLAG_BMASK) { if (ctx->hflags & MIPS_HFLAG_BMASK) {
if (!(ctx->hflags & (MIPS_HFLAG_BDS16 | MIPS_HFLAG_BDS32 | if (!(ctx->hflags & (MIPS_HFLAG_BDS16 | MIPS_HFLAG_BDS32 |
MIPS_HFLAG_FBNSLOT))) { MIPS_HFLAG_FBNSLOT))) {
/* force to generate branch as there is neither delay nor /*
forbidden slot */ * Force to generate branch as there is neither delay nor
* forbidden slot.
*/
is_slot = 1; is_slot = 1;
} }
if ((ctx->hflags & MIPS_HFLAG_M16) && if ((ctx->hflags & MIPS_HFLAG_M16) &&
(ctx->hflags & MIPS_HFLAG_FBNSLOT)) { (ctx->hflags & MIPS_HFLAG_FBNSLOT)) {
/* Force to generate branch as microMIPS R6 doesn't restrict /*
branches in the forbidden slot. */ * Force to generate branch as microMIPS R6 doesn't restrict
* branches in the forbidden slot.
*/
is_slot = 1; is_slot = 1;
} }
} }
@ -30126,10 +30243,12 @@ static void mips_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
return; return;
} }
/* Execute a branch and its delay slot as a single instruction. /*
This is what GDB expects and is consistent with what the * Execute a branch and its delay slot as a single instruction.
hardware does (e.g. if a delay slot instruction faults, the * This is what GDB expects and is consistent with what the
reported PC is the PC of the branch). */ * hardware does (e.g. if a delay slot instruction faults, the
* reported PC is the PC of the branch).
*/
if (ctx->base.singlestep_enabled && if (ctx->base.singlestep_enabled &&
(ctx->hflags & MIPS_HFLAG_BMASK) == 0) { (ctx->hflags & MIPS_HFLAG_BMASK) == 0) {
ctx->base.is_jmp = DISAS_TOO_MANY; ctx->base.is_jmp = DISAS_TOO_MANY;
@ -30255,8 +30374,10 @@ void mips_tcg_init(struct uc_struct *uc)
int off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[0]); int off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[0]);
tcg_ctx->msa_wr_d[i * 2] = tcg_ctx->msa_wr_d[i * 2] =
tcg_global_mem_new_i64(tcg_ctx, tcg_ctx->cpu_env, off, msaregnames[i * 2]); tcg_global_mem_new_i64(tcg_ctx, tcg_ctx->cpu_env, off, msaregnames[i * 2]);
/* The scalar floating-point unit (FPU) registers are mapped on /*
* the MSA vector registers. */ * The scalar floating-point unit (FPU) registers are mapped on
* the MSA vector registers.
*/
tcg_ctx->fpu_f64[i] = tcg_ctx->msa_wr_d[i * 2]; tcg_ctx->fpu_f64[i] = tcg_ctx->msa_wr_d[i * 2];
off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[1]); off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[1]);
tcg_ctx->msa_wr_d[i * 2 + 1] = tcg_ctx->msa_wr_d[i * 2 + 1] =
@ -30422,8 +30543,10 @@ void cpu_state_reset(CPUMIPSState *env)
/* Enable 64-bit address mode. */ /* Enable 64-bit address mode. */
env->CP0_Status |= (1 << CP0St_UX); env->CP0_Status |= (1 << CP0St_UX);
# endif # endif
/* Enable access to the CPUNum, SYNCI_Step, CC, and CCRes RDHWR /*
hardware registers. */ * Enable access to the CPUNum, SYNCI_Step, CC, and CCRes RDHWR
* hardware registers.
*/
env->CP0_HWREna |= 0x0000000F; env->CP0_HWREna |= 0x0000000F;
if (env->CP0_Config1 & (1 << CP0C1_FP)) { if (env->CP0_Config1 & (1 << CP0C1_FP)) {
env->CP0_Status |= (1 << CP0St_CU1); env->CP0_Status |= (1 << CP0St_CU1);
@ -30440,8 +30563,10 @@ void cpu_state_reset(CPUMIPSState *env)
# endif # endif
#else #else
if (env->hflags & MIPS_HFLAG_BMASK) { if (env->hflags & MIPS_HFLAG_BMASK) {
/* If the exception was raised from a delay slot, /*
come back to the jump. */ * If the exception was raised from a delay slot,
* come back to the jump.
*/
env->CP0_ErrorEPC = (env->active_tc.PC env->CP0_ErrorEPC = (env->active_tc.PC
- (env->hflags & MIPS_HFLAG_B16 ? 2 : 4)); - (env->hflags & MIPS_HFLAG_B16 ? 2 : 4));
} else { } else {
@ -30460,8 +30585,10 @@ void cpu_state_reset(CPUMIPSState *env)
env->CP0_EntryHi_ASID_mask = (env->CP0_Config4 & (1 << CP0C4_AE)) ? env->CP0_EntryHi_ASID_mask = (env->CP0_Config4 & (1 << CP0C4_AE)) ?
0x3ff : 0xff; 0x3ff : 0xff;
env->CP0_Status = (1 << CP0St_BEV) | (1 << CP0St_ERL); env->CP0_Status = (1 << CP0St_BEV) | (1 << CP0St_ERL);
/* vectored interrupts not implemented, timer on int 7, /*
no performance counters. */ * Vectored interrupts not implemented, timer on int 7,
* no performance counters.
*/
env->CP0_IntCtl = 0xe0000000; env->CP0_IntCtl = 0xe0000000;
{ {
int i; int i;