yuzu/unicorn
1
0
Fork 0
mirror of https://github.com/yuzu-emu/unicorn.git synced 2025-04-01 23:07:03 +00:00
Code Issues Packages Projects Releases Wiki Activity

target/arm: Move cpu_mmu_index out of line

Browse source 
This function is, or will shortly become, too big to inline.

Backports commit 65e4655c609a4a2fd428459d3efb62b704488fd6 from qemu
This commit is contained in:
Richard Henderson 2019-01-22 16:02:35 -05:00 committed by Lioncash
parent 5de5903d1c
commit 8856234574
No known key found for this signature in database
GPG key ID: 4E3C3CC1031BA9C7
7 changed files with 64 additions and 46 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
qemu/aarch64.h
View file

@ -3280,6 +3280,8 @@
#define arm64_reg_reset arm64_reg_reset_aarch64
#define arm64_reg_write arm64_reg_write_aarch64
#define arm64_release arm64_release_aarch64
#define arm_v7m_mmu_idx_for_secstate arm_v7m_mmu_idx_for_secstate_aarch64
#define arm_v7m_mmu_idx_for_secstate_and_priv arm_v7m_mmu_idx_for_secstate_and_priv_aarch64
#define arm_hcr_el2_eff arm_hcr_el2_eff_aarch64
#define arm_regime_tbi0 arm_regime_tbi0_aarch64
#define arm_regime_tbi1 arm_regime_tbi1_aarch64

2
qemu/aarch64eb.h
View file

@ -3280,6 +3280,8 @@
#define arm64_reg_reset arm64_reg_reset_aarch64eb
#define arm64_reg_write arm64_reg_write_aarch64eb
#define arm64_release arm64_release_aarch64eb
#define arm_v7m_mmu_idx_for_secstate arm_v7m_mmu_idx_for_secstate_aarch64eb
#define arm_v7m_mmu_idx_for_secstate_and_priv arm_v7m_mmu_idx_for_secstate_and_priv_aarch64eb
#define arm_hcr_el2_eff arm_hcr_el2_eff_aarch64eb
#define arm_regime_tbi0 arm_regime_tbi0_aarch64eb
#define arm_regime_tbi1 arm_regime_tbi1_aarch64eb

2
qemu/arm.h
View file

@ -3271,6 +3271,8 @@
#define xscale_cp_reginfo xscale_cp_reginfo_arm
#define xscale_cpar_write xscale_cpar_write_arm
#define aarch64_translator_ops aarch64_translator_ops_arm
#define arm_v7m_mmu_idx_for_secstate arm_v7m_mmu_idx_for_secstate_arm
#define arm_v7m_mmu_idx_for_secstate_and_priv arm_v7m_mmu_idx_for_secstate_and_priv_arm
#define ARM_REGS_STORAGE_SIZE ARM_REGS_STORAGE_SIZE_arm
#define arm_hcr_el2_eff arm_hcr_el2_eff_arm
#define arm_regime_tbi0 arm_regime_tbi0_arm

2
qemu/armeb.h
View file

@ -3271,6 +3271,8 @@
#define xscale_cp_reginfo xscale_cp_reginfo_armeb
#define xscale_cpar_write xscale_cpar_write_armeb
#define aarch64_translator_ops aarch64_translator_ops_armeb
#define arm_v7m_mmu_idx_for_secstate arm_v7m_mmu_idx_for_secstate_armeb
#define arm_v7m_mmu_idx_for_secstate_and_priv arm_v7m_mmu_idx_for_secstate_and_priv_armeb
#define ARM_REGS_STORAGE_SIZE ARM_REGS_STORAGE_SIZE_armeb
#define arm_hcr_el2_eff arm_hcr_el2_eff_armeb
#define arm_regime_tbi0 arm_regime_tbi0_armeb

4
qemu/header_gen.py
View file

@ -3280,6 +3280,8 @@ symbols = (
arm_symbols = (
'aarch64_translator_ops',
'arm_v7m_mmu_idx_for_secstate',
'arm_v7m_mmu_idx_for_secstate_and_priv',
'ARM_REGS_STORAGE_SIZE',
'arm_hcr_el2_eff',
'arm_regime_tbi0',
@ -3315,6 +3317,8 @@ aarch64_symbols = (
'arm64_reg_reset',
'arm64_reg_write',
'arm64_release',
'arm_v7m_mmu_idx_for_secstate',
'arm_v7m_mmu_idx_for_secstate_and_priv',
'arm_hcr_el2_eff',
'arm_regime_tbi0',
'arm_regime_tbi1',

51
qemu/target/arm/cpu.h
View file

@ -2730,57 +2730,16 @@ static inline int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx)
}
/* Return the MMU index for a v7M CPU in the specified security and
* privilege state
* privilege state.
*/
static inline ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env,
bool secstate,
bool priv)
{
ARMMMUIdx mmu_idx = ARM_MMU_IDX_M;
if (priv) {
mmu_idx |= ARM_MMU_IDX_M_PRIV;
}
// Unicorn: if'd out
#if 0
if (armv7m_nvic_neg_prio_requested(env->nvic, secstate)) {
mmu_idx |= ARM_MMU_IDX_M_NEGPRI;
}
#endif
if (secstate) {
mmu_idx |= ARM_MMU_IDX_M_S;
}
return mmu_idx;
}
ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env,
bool secstate, bool priv);
/* Return the MMU index for a v7M CPU in the specified security state */
static inline ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env,
bool secstate)
{
bool priv = arm_current_el(env) != 0;
return arm_v7m_mmu_idx_for_secstate_and_priv(env, secstate, priv);
}
ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate);
/* Determine the current mmu_idx to use for normal loads/stores */
static inline int cpu_mmu_index(CPUARMState *env, bool ifetch)
{
int el = arm_current_el(env);
if (arm_feature(env, ARM_FEATURE_M)) {
ARMMMUIdx mmu_idx = arm_v7m_mmu_idx_for_secstate(env, env->v7m.secure);
return arm_to_core_mmu_idx(mmu_idx);
}
if (el < 2 && arm_is_secure_below_el3(env)) {
return arm_to_core_mmu_idx(ARMMMUIdx_S1SE0 + el);
}
return el;
}
int cpu_mmu_index(CPUARMState *env, bool ifetch);
/* Indexes used when registering address spaces with cpu_address_space_init */
typedef enum ARMASIdx {

47
qemu/target/arm/helper.c
View file

@ -12153,6 +12153,53 @@ int fp_exception_el(CPUARMState *env, int cur_el)
return 0;
}
ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env,
bool secstate, bool priv)
{
ARMMMUIdx mmu_idx = ARM_MMU_IDX_M;
if (priv) {
mmu_idx |= ARM_MMU_IDX_M_PRIV;
}
// Unicorn: disabled
#if 0
if (armv7m_nvic_neg_prio_requested(env->nvic, secstate)) {
mmu_idx |= ARM_MMU_IDX_M_NEGPRI;
}
#endif
if (secstate) {
mmu_idx |= ARM_MMU_IDX_M_S;
}
return mmu_idx;
}
/* Return the MMU index for a v7M CPU in the specified security state */
ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate)
{
bool priv = arm_current_el(env) != 0;
return arm_v7m_mmu_idx_for_secstate_and_priv(env, secstate, priv);
}
int cpu_mmu_index(CPUARMState *env, bool ifetch)
{
int el = arm_current_el(env);
if (arm_feature(env, ARM_FEATURE_M)) {
ARMMMUIdx mmu_idx = arm_v7m_mmu_idx_for_secstate(env, env->v7m.secure);
return arm_to_core_mmu_idx(mmu_idx);
}
if (el < 2 && arm_is_secure_below_el3(env)) {
return arm_to_core_mmu_idx(ARMMMUIdx_S1SE0 + el);
}
return el;
}
void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
target_ulong *cs_base, uint32_t *pflags)
{