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target/arm: expose MPIDR_EL1 to userspace

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As this is a single register we could expose it with a simple ifdef
but we use the existing modify_arm_cp_regs mechanism for consistency.

Backports commit 522641660c3de64ed8322b8636c58625cd564a3f from qemu
This commit is contained in:
Alex Bennée 2019-02-15 17:29:21 -05:00 committed by Lioncash
parent babf31dfa0
commit 890983f186
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 14 additions and 7 deletions
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21
qemu/target/arm/helper.c
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@ -3222,13 +3222,6 @@ static uint64_t mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
return mpidr_read_val(env); return mpidr_read_val(env);
} }
static const ARMCPRegInfo mpidr_cp_reginfo[] = {
{ "MPIDR", 0,0,0, 3,0,5, ARM_CP_STATE_BOTH,
ARM_CP_NO_RAW, PL1_R, 0, NULL, 0, 0, {0, 0},
NULL, mpidr_read, },
REGINFO_SENTINEL
};
static const ARMCPRegInfo lpae_cp_reginfo[] = { static const ARMCPRegInfo lpae_cp_reginfo[] = {
/* NOP AMAIR0/1 */ /* NOP AMAIR0/1 */
{ "AMAIR0", 0,10,3, 3,0,0, ARM_CP_STATE_BOTH, { "AMAIR0", 0,10,3, 3,0,0, ARM_CP_STATE_BOTH,
@ -5590,6 +5583,20 @@ void register_cp_regs_for_features(ARMCPU *cpu)
} }
if (arm_feature(env, ARM_FEATURE_MPIDR)) { if (arm_feature(env, ARM_FEATURE_MPIDR)) {
ARMCPRegInfo mpidr_cp_reginfo[] = {
{ .name = "MPIDR_EL1", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5,
.access = PL1_R, .readfn = mpidr_read, .type = ARM_CP_NO_RAW },
REGINFO_SENTINEL
};
#ifdef CONFIG_USER_ONLY
ARMCPRegUserSpaceInfo mpidr_user_cp_reginfo[] = {
{ .name = "MPIDR_EL1",
.fixed_bits = 0x0000000080000000 },
REGUSERINFO_SENTINEL
};
modify_arm_cp_regs(mpidr_cp_reginfo, mpidr_user_cp_reginfo);
#endif
define_arm_cp_regs(cpu, mpidr_cp_reginfo); define_arm_cp_regs(cpu, mpidr_cp_reginfo);
} }