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unicorn/aarch64: Lessen the amount of ARMCPU macro usages

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This macro can just be used once per function that it's used in,
reducing the overall amount of line noise in register reading and writing
This commit is contained in:
Lioncash 2018-03-07 09:54:32 -05:00
parent f425b6aa81
commit 890f234a53
No known key found for this signature in database
GPG key ID: 4E3C3CC1031BA9C7
2 changed files with 71 additions and 68 deletions
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84
qemu/target/arm/unicorn_aarch64.c
View file

@ -47,6 +47,7 @@ void arm64_reg_reset(struct uc_struct *uc)
int arm64_reg_read(struct uc_struct *uc, unsigned int *regs, void **vals, int count)
{
CPUState *mycpu = uc->cpu;
CPUARMState *state = &ARM_CPU(uc, mycpu)->env;
int i;
for (i = 0; i < count; i++) {
@ -57,63 +58,63 @@ int arm64_reg_read(struct uc_struct *uc, unsigned int *regs, void **vals, int co
regid += UC_ARM64_REG_Q0 - UC_ARM64_REG_V0;
}
if (regid >= UC_ARM64_REG_X0 && regid <= UC_ARM64_REG_X28) {
*(int64_t *)value = ARM_CPU(uc, mycpu)->env.xregs[regid - UC_ARM64_REG_X0];
*(int64_t *)value = state->xregs[regid - UC_ARM64_REG_X0];
} else if (regid >= UC_ARM64_REG_W0 && regid <= UC_ARM64_REG_W30) {
*(int32_t *)value = READ_DWORD(ARM_CPU(uc, mycpu)->env.xregs[regid - UC_ARM64_REG_W0]);
*(int32_t *)value = READ_DWORD(state->xregs[regid - UC_ARM64_REG_W0]);
} else if (regid >= UC_ARM64_REG_Q0 && regid <= UC_ARM64_REG_Q31) {
float64 *dst = (float64*) value;
uint32_t reg_index = 2*(regid - UC_ARM64_REG_Q0);
dst[0] = ARM_CPU(uc, mycpu)->env.vfp.regs[reg_index];
dst[1] = ARM_CPU(uc, mycpu)->env.vfp.regs[reg_index+1];
dst[0] = state->vfp.regs[reg_index];
dst[1] = state->vfp.regs[reg_index+1];
} else if (regid >= UC_ARM64_REG_D0 && regid <= UC_ARM64_REG_D31) {
*(float64*)value = ARM_CPU(uc, mycpu)->env.vfp.regs[2*(regid - UC_ARM64_REG_D0)];
*(float64*)value = state->vfp.regs[2*(regid - UC_ARM64_REG_D0)];
} else if (regid >= UC_ARM64_REG_S0 && regid <= UC_ARM64_REG_S31) {
*(int32_t*)value = READ_DWORD(ARM_CPU(uc, mycpu)->env.vfp.regs[2*(regid - UC_ARM64_REG_S0)]);
*(int32_t*)value = READ_DWORD(state->vfp.regs[2*(regid - UC_ARM64_REG_S0)]);
} else if (regid >= UC_ARM64_REG_H0 && regid <= UC_ARM64_REG_H31) {
*(int16_t*)value = READ_WORD(ARM_CPU(uc, mycpu)->env.vfp.regs[2*(regid - UC_ARM64_REG_H0)]);
*(int16_t*)value = READ_WORD(state->vfp.regs[2*(regid - UC_ARM64_REG_H0)]);
} else if (regid >= UC_ARM64_REG_B0 && regid <= UC_ARM64_REG_B31) {
*(int8_t*)value = READ_BYTE_L(ARM_CPU(uc, mycpu)->env.vfp.regs[2*(regid - UC_ARM64_REG_B0)]);
*(int8_t*)value = READ_BYTE_L(state->vfp.regs[2*(regid - UC_ARM64_REG_B0)]);
} else {
switch(regid) {
default: break;
case UC_ARM64_REG_CPACR_EL1:
*(uint32_t *)value = ARM_CPU(uc, mycpu)->env.cp15.cpacr_el1;
*(uint32_t *)value = state->cp15.cpacr_el1;
break;
case UC_ARM64_REG_ESR:
*(uint32_t *)value = ARM_CPU(uc, mycpu)->env.exception.syndrome;
*(uint32_t *)value = state->exception.syndrome;
break;
case UC_ARM64_REG_TPIDR_EL0:
*(int64_t *)value = ARM_CPU(uc, mycpu)->env.cp15.tpidr_el[0];
*(int64_t *)value = state->cp15.tpidr_el[0];
break;
case UC_ARM64_REG_TPIDRRO_EL0:
*(int64_t *)value = ARM_CPU(uc, mycpu)->env.cp15.tpidrro_el[0];
*(int64_t *)value = state->cp15.tpidrro_el[0];
break;
case UC_ARM64_REG_TPIDR_EL1:
*(int64_t *)value = ARM_CPU(uc, mycpu)->env.cp15.tpidr_el[1];
*(int64_t *)value = state->cp15.tpidr_el[1];
break;
case UC_ARM64_REG_X29:
*(int64_t *)value = ARM_CPU(uc, mycpu)->env.xregs[29];
*(int64_t *)value = state->xregs[29];
break;
case UC_ARM64_REG_X30:
*(int64_t *)value = ARM_CPU(uc, mycpu)->env.xregs[30];
*(int64_t *)value = state->xregs[30];
break;
case UC_ARM64_REG_PC:
*(uint64_t *)value = ARM_CPU(uc, mycpu)->env.pc;
*(uint64_t *)value = state->pc;
break;
case UC_ARM64_REG_SP:
*(int64_t *)value = ARM_CPU(uc, mycpu)->env.xregs[31];
*(int64_t *)value = state->xregs[31];
break;
case UC_ARM64_REG_NZCV:
*(int32_t *)value = cpsr_read(&ARM_CPU(uc, mycpu)->env) & CPSR_NZCV;
*(int32_t *)value = cpsr_read(state) & CPSR_NZCV;
break;
case UC_ARM64_REG_PSTATE:
*(uint32_t *)value = pstate_read(&ARM_CPU(uc, mycpu)->env);
*(uint32_t *)value = pstate_read(state);
break;
case UC_ARM64_REG_FPCR:
*(uint32_t *)value = vfp_get_fpcr(&ARM_CPU(uc, mycpu)->env);
*(uint32_t *)value = vfp_get_fpcr(state);
break;
case UC_ARM64_REG_FPSR:
*(uint32_t *)value = vfp_get_fpsr(&ARM_CPU(uc, mycpu)->env);
*(uint32_t *)value = vfp_get_fpsr(state);
break;
}
}
@ -125,6 +126,7 @@ int arm64_reg_read(struct uc_struct *uc, unsigned int *regs, void **vals, int co
int arm64_reg_write(struct uc_struct *uc, unsigned int *regs, void* const* vals, int count)
{
CPUState *mycpu = uc->cpu;
CPUARMState *state = &ARM_CPU(uc, mycpu)->env;
int i;
for (i = 0; i < count; i++) {
@ -134,63 +136,63 @@ int arm64_reg_write(struct uc_struct *uc, unsigned int *regs, void* const* vals,
regid += UC_ARM64_REG_Q0 - UC_ARM64_REG_V0;
}
if (regid >= UC_ARM64_REG_X0 && regid <= UC_ARM64_REG_X28) {
ARM_CPU(uc, mycpu)->env.xregs[regid - UC_ARM64_REG_X0] = *(uint64_t *)value;
state->xregs[regid - UC_ARM64_REG_X0] = *(uint64_t *)value;
} else if (regid >= UC_ARM64_REG_W0 && regid <= UC_ARM64_REG_W30) {
WRITE_DWORD(ARM_CPU(uc, mycpu)->env.xregs[regid - UC_ARM64_REG_W0], *(uint32_t *)value);
WRITE_DWORD(state->xregs[regid - UC_ARM64_REG_W0], *(uint32_t *)value);
} else if (regid >= UC_ARM64_REG_Q0 && regid <= UC_ARM64_REG_Q31) {
float64 *src = (float64*) value;
uint32_t reg_index = 2*(regid - UC_ARM64_REG_Q0);
ARM_CPU(uc, mycpu)->env.vfp.regs[reg_index] = src[0];
ARM_CPU(uc, mycpu)->env.vfp.regs[reg_index+1] = src[1];
state->vfp.regs[reg_index] = src[0];
state->vfp.regs[reg_index+1] = src[1];
} else if (regid >= UC_ARM64_REG_D0 && regid <= UC_ARM64_REG_D31) {
ARM_CPU(uc, mycpu)->env.vfp.regs[2*(regid - UC_ARM64_REG_D0)] = * (float64*) value;
state->vfp.regs[2*(regid - UC_ARM64_REG_D0)] = * (float64*) value;
} else if (regid >= UC_ARM64_REG_S0 && regid <= UC_ARM64_REG_S31) {
WRITE_DWORD(ARM_CPU(uc, mycpu)->env.vfp.regs[2*(regid - UC_ARM64_REG_S0)], *(int32_t*) value);
WRITE_DWORD(state->vfp.regs[2*(regid - UC_ARM64_REG_S0)], *(int32_t*) value);
} else if (regid >= UC_ARM64_REG_H0 && regid <= UC_ARM64_REG_H31) {
WRITE_WORD(ARM_CPU(uc, mycpu)->env.vfp.regs[2*(regid - UC_ARM64_REG_H0)], *(int16_t*) value);
WRITE_WORD(state->vfp.regs[2*(regid - UC_ARM64_REG_H0)], *(int16_t*) value);
} else if (regid >= UC_ARM64_REG_B0 && regid <= UC_ARM64_REG_B31) {
WRITE_BYTE_L(ARM_CPU(uc, mycpu)->env.vfp.regs[2*(regid - UC_ARM64_REG_B0)], *(int8_t*) value);
WRITE_BYTE_L(state->vfp.regs[2*(regid - UC_ARM64_REG_B0)], *(int8_t*) value);
} else {
switch(regid) {
default: break;
case UC_ARM64_REG_CPACR_EL1:
ARM_CPU(uc, mycpu)->env.cp15.cpacr_el1 = *(uint32_t *)value;
state->cp15.cpacr_el1 = *(uint32_t *)value;
break;
case UC_ARM64_REG_TPIDR_EL0:
ARM_CPU(uc, mycpu)->env.cp15.tpidr_el[0] = *(uint64_t *)value;
state->cp15.tpidr_el[0] = *(uint64_t *)value;
break;
case UC_ARM64_REG_TPIDRRO_EL0:
ARM_CPU(uc, mycpu)->env.cp15.tpidrro_el[0] = *(uint64_t *)value;
state->cp15.tpidrro_el[0] = *(uint64_t *)value;
break;
case UC_ARM64_REG_TPIDR_EL1:
ARM_CPU(uc, mycpu)->env.cp15.tpidr_el[1] = *(uint64_t *)value;
state->cp15.tpidr_el[1] = *(uint64_t *)value;
break;
case UC_ARM64_REG_X29:
ARM_CPU(uc, mycpu)->env.xregs[29] = *(uint64_t *)value;
state->xregs[29] = *(uint64_t *)value;
break;
case UC_ARM64_REG_X30:
ARM_CPU(uc, mycpu)->env.xregs[30] = *(uint64_t *)value;
state->xregs[30] = *(uint64_t *)value;
break;
case UC_ARM64_REG_PC:
ARM_CPU(uc, mycpu)->env.pc = *(uint64_t *)value;
state->pc = *(uint64_t *)value;
// force to quit execution and flush TB
uc->quit_request = true;
uc_emu_stop(uc);
break;
case UC_ARM64_REG_SP:
ARM_CPU(uc, mycpu)->env.xregs[31] = *(uint64_t *)value;
state->xregs[31] = *(uint64_t *)value;
break;
case UC_ARM64_REG_NZCV:
cpsr_write(&ARM_CPU(uc, mycpu)->env, *(uint32_t *) value, CPSR_NZCV, CPSRWriteRaw);
cpsr_write(state, *(uint32_t *) value, CPSR_NZCV, CPSRWriteRaw);
break;
case UC_ARM64_REG_PSTATE:
pstate_write(&ARM_CPU(uc, mycpu)->env, *(uint32_t *)value);
pstate_write(state, *(uint32_t *)value);
break;
case UC_ARM64_REG_FPCR:
vfp_set_fpcr(&ARM_CPU(uc, mycpu)->env, *(uint32_t *)value);
vfp_set_fpcr(state, *(uint32_t *)value);
break;
case UC_ARM64_REG_FPSR:
vfp_set_fpsr(&ARM_CPU(uc, mycpu)->env, *(uint32_t *)value);
vfp_set_fpsr(state, *(uint32_t *)value);
break;
}
}

55
qemu/target/arm/unicorn_arm.c
View file

@ -50,46 +50,45 @@ void arm_reg_reset(struct uc_struct *uc)
int arm_reg_read(struct uc_struct *uc, unsigned int *regs, void **vals, int count)
{
CPUState *mycpu;
CPUState *mycpu = uc->cpu;
CPUARMState *state = &ARM_CPU(uc, mycpu)->env;
int i;
mycpu = uc->cpu;
for (i = 0; i < count; i++) {
unsigned int regid = regs[i];
void *value = vals[i];
if (regid >= UC_ARM_REG_R0 && regid <= UC_ARM_REG_R12)
*(int32_t *)value = ARM_CPU(uc, mycpu)->env.regs[regid - UC_ARM_REG_R0];
*(int32_t *)value = state->regs[regid - UC_ARM_REG_R0];
else if (regid >= UC_ARM_REG_D0 && regid <= UC_ARM_REG_D31)
*(float64 *)value = ARM_CPU(uc, mycpu)->env.vfp.regs[regid - UC_ARM_REG_D0];
*(float64 *)value = state->vfp.regs[regid - UC_ARM_REG_D0];
else {
switch(regid) {
case UC_ARM_REG_APSR:
*(int32_t *)value = cpsr_read(&ARM_CPU(uc, mycpu)->env) & CPSR_NZCV;
*(int32_t *)value = cpsr_read(state) & CPSR_NZCV;
break;
case UC_ARM_REG_CPSR:
*(int32_t *)value = cpsr_read(&ARM_CPU(uc, mycpu)->env);
*(int32_t *)value = cpsr_read(state);
break;
//case UC_ARM_REG_SP:
case UC_ARM_REG_R13:
*(int32_t *)value = ARM_CPU(uc, mycpu)->env.regs[13];
*(int32_t *)value = state->regs[13];
break;
//case UC_ARM_REG_LR:
case UC_ARM_REG_R14:
*(int32_t *)value = ARM_CPU(uc, mycpu)->env.regs[14];
*(int32_t *)value = state->regs[14];
break;
//case UC_ARM_REG_PC:
case UC_ARM_REG_R15:
*(int32_t *)value = ARM_CPU(uc, mycpu)->env.regs[15];
*(int32_t *)value = state->regs[15];
break;
case UC_ARM_REG_C1_C0_2:
*(int32_t *)value = ARM_CPU(uc, mycpu)->env.cp15.cpacr_el1;
*(int32_t *)value = state->cp15.cpacr_el1;
break;
case UC_ARM_REG_C13_C0_3:
*(int32_t *)value = ARM_CPU(uc, mycpu)->env.cp15.tpidrro_el[0];
*(int32_t *)value = state->cp15.tpidrro_el[0];
break;
case UC_ARM_REG_FPEXC:
*(int32_t *)value = ARM_CPU(uc, mycpu)->env.vfp.xregs[ARM_VFP_FPEXC];
*(int32_t *)value = state->vfp.xregs[ARM_VFP_FPEXC];
break;
}
}
@ -101,51 +100,52 @@ int arm_reg_read(struct uc_struct *uc, unsigned int *regs, void **vals, int coun
int arm_reg_write(struct uc_struct *uc, unsigned int *regs, void* const* vals, int count)
{
CPUState *mycpu = uc->cpu;
CPUARMState *state = &ARM_CPU(uc, mycpu)->env;
int i;
for (i = 0; i < count; i++) {
unsigned int regid = regs[i];
const void *value = vals[i];
if (regid >= UC_ARM_REG_R0 && regid <= UC_ARM_REG_R12)
ARM_CPU(uc, mycpu)->env.regs[regid - UC_ARM_REG_R0] = *(uint32_t *)value;
state->regs[regid - UC_ARM_REG_R0] = *(uint32_t *)value;
else if (regid >= UC_ARM_REG_D0 && regid <= UC_ARM_REG_D31)
ARM_CPU(uc, mycpu)->env.vfp.regs[regid - UC_ARM_REG_D0] = *(float64 *)value;
state->vfp.regs[regid - UC_ARM_REG_D0] = *(float64 *)value;
else {
switch(regid) {
case UC_ARM_REG_APSR:
cpsr_write(&ARM_CPU(uc, mycpu)->env, *(uint32_t *)value, CPSR_NZCV, CPSRWriteRaw);
cpsr_write(state, *(uint32_t *)value, CPSR_NZCV, CPSRWriteRaw);
break;
case UC_ARM_REG_CPSR:
cpsr_write(&ARM_CPU(uc, mycpu)->env, *(uint32_t *)value, ~0, CPSRWriteRaw);
cpsr_write(state, *(uint32_t *)value, ~0, CPSRWriteRaw);
break;
//case UC_ARM_REG_SP:
case UC_ARM_REG_R13:
ARM_CPU(uc, mycpu)->env.regs[13] = *(uint32_t *)value;
state->regs[13] = *(uint32_t *)value;
break;
//case UC_ARM_REG_LR:
case UC_ARM_REG_R14:
ARM_CPU(uc, mycpu)->env.regs[14] = *(uint32_t *)value;
state->regs[14] = *(uint32_t *)value;
break;
//case UC_ARM_REG_PC:
case UC_ARM_REG_R15:
ARM_CPU(uc, mycpu)->env.pc = (*(uint32_t *)value & ~1);
ARM_CPU(uc, mycpu)->env.thumb = (*(uint32_t *)value & 1);
ARM_CPU(uc, mycpu)->env.uc->thumb = (*(uint32_t *)value & 1);
ARM_CPU(uc, mycpu)->env.regs[15] = (*(uint32_t *)value & ~1);
state->pc = (*(uint32_t *)value & ~1);
state->thumb = (*(uint32_t *)value & 1);
state->uc->thumb = (*(uint32_t *)value & 1);
state->regs[15] = (*(uint32_t *)value & ~1);
// force to quit execution and flush TB
uc->quit_request = true;
uc_emu_stop(uc);
break;
case UC_ARM_REG_C1_C0_2:
ARM_CPU(uc, mycpu)->env.cp15.cpacr_el1 = *(int32_t *)value;
state->cp15.cpacr_el1 = *(int32_t *)value;
break;
case UC_ARM_REG_C13_C0_3:
ARM_CPU(uc, mycpu)->env.cp15.tpidrro_el[0] = *(int32_t *)value;
state->cp15.tpidrro_el[0] = *(int32_t *)value;
break;
case UC_ARM_REG_FPEXC:
ARM_CPU(uc, mycpu)->env.vfp.xregs[ARM_VFP_FPEXC] = *(int32_t *)value;
state->vfp.xregs[ARM_VFP_FPEXC] = *(int32_t *)value;
break;
}
}
@ -168,6 +168,7 @@ static bool arm_stop_interrupt(int intno)
static uc_err arm_query(struct uc_struct *uc, uc_query_type type, size_t *result)
{
CPUState *mycpu = uc->cpu;
CPUARMState *state = &ARM_CPU(uc, mycpu)->env;
uint32_t mode;
switch(type) {
@ -175,7 +176,7 @@ static uc_err arm_query(struct uc_struct *uc, uc_query_type type, size_t *result
// zero out ARM/THUMB mode
mode = uc->mode & ~(UC_MODE_ARM | UC_MODE_THUMB);
// THUMB mode or ARM MOde
mode += ((ARM_CPU(uc, mycpu)->env.thumb != 0)? UC_MODE_THUMB : UC_MODE_ARM);
mode += ((state->thumb != 0) ? UC_MODE_THUMB : UC_MODE_ARM);
*result = mode;
return UC_ERR_OK;
default: