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target/mips: Add emulation of non-MXU MULL within MXU decoding engine
Backports commit 11d56f61036091206f085e58cff72b6872911d3a from qemu
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@ -1642,7 +1642,7 @@ enum {
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enum {
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enum {
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OPC_MXU_S32MADD = 0x00,
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OPC_MXU_S32MADD = 0x00,
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OPC_MXU_S32MADDU = 0x01,
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OPC_MXU_S32MADDU = 0x01,
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/* not assigned 0x02 */
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OPC__MXU_MUL = 0x02,
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OPC_MXU__POOL00 = 0x03,
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OPC_MXU__POOL00 = 0x03,
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OPC_MXU_S32MSUB = 0x04,
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OPC_MXU_S32MSUB = 0x04,
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OPC_MXU_S32MSUBU = 0x05,
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OPC_MXU_S32MSUBU = 0x05,
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@ -25051,6 +25051,11 @@ static void decode_opc_mxu__pool20(CPUMIPSState *env, DisasContext *ctx)
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*/
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*/
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static void decode_opc_mxu(CPUMIPSState *env, DisasContext *ctx)
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static void decode_opc_mxu(CPUMIPSState *env, DisasContext *ctx)
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{
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{
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/*
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* TODO: Investigate necessity of including handling of
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* CLZ, CLO, SDBB in this function, as they belong to
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* SPECIAL2 opcode space for regular pre-R6 MIPS ISAs.
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*/
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uint32_t opcode = extract32(ctx->opcode, 0, 6);
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uint32_t opcode = extract32(ctx->opcode, 0, 6);
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switch (opcode) {
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switch (opcode) {
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@ -25064,6 +25069,18 @@ static void decode_opc_mxu(CPUMIPSState *env, DisasContext *ctx)
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MIPS_INVAL("OPC_MXU_S32MADDU");
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MIPS_INVAL("OPC_MXU_S32MADDU");
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generate_exception_end(ctx, EXCP_RI);
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generate_exception_end(ctx, EXCP_RI);
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break;
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break;
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case OPC__MXU_MUL: /* 0x2 - unused in MXU specs */
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{
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uint32_t rs, rt, rd, op1;
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rs = extract32(ctx->opcode, 21, 5);
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rt = extract32(ctx->opcode, 16, 5);
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rd = extract32(ctx->opcode, 11, 5);
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op1 = MASK_SPECIAL2(ctx->opcode);
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gen_arith(ctx, op1, rd, rs, rt);
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}
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break;
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case OPC_MXU__POOL00:
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case OPC_MXU__POOL00:
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decode_opc_mxu__pool00(env, ctx);
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decode_opc_mxu__pool00(env, ctx);
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break;
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break;
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