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target/mips: Add emulation of non-MXU MULL within MXU decoding engine

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Backports commit 11d56f61036091206f085e58cff72b6872911d3a from qemu
This commit is contained in:
Craig Janeczek 2018-11-11 06:05:41 -05:00 committed by Lioncash
parent 839f5babde
commit 8a03757fb0
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 18 additions and 1 deletions
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19
qemu/target/mips/translate.c
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@ -1642,7 +1642,7 @@ enum {
enum {
OPC_MXU_S32MADD = 0x00,
OPC_MXU_S32MADDU = 0x01,
/* not assigned 0x02 */
OPC__MXU_MUL = 0x02,
OPC_MXU__POOL00 = 0x03,
OPC_MXU_S32MSUB = 0x04,
OPC_MXU_S32MSUBU = 0x05,
@ -25051,6 +25051,11 @@ static void decode_opc_mxu__pool20(CPUMIPSState *env, DisasContext *ctx)
*/
static void decode_opc_mxu(CPUMIPSState *env, DisasContext *ctx)
{
/*
* TODO: Investigate necessity of including handling of
* CLZ, CLO, SDBB in this function, as they belong to
* SPECIAL2 opcode space for regular pre-R6 MIPS ISAs.
*/
uint32_t opcode = extract32(ctx->opcode, 0, 6);
switch (opcode) {
@ -25064,6 +25069,18 @@ static void decode_opc_mxu(CPUMIPSState *env, DisasContext *ctx)
MIPS_INVAL("OPC_MXU_S32MADDU");
generate_exception_end(ctx, EXCP_RI);
break;
case OPC__MXU_MUL: /* 0x2 - unused in MXU specs */
{
uint32_t rs, rt, rd, op1;
rs = extract32(ctx->opcode, 21, 5);
rt = extract32(ctx->opcode, 16, 5);
rd = extract32(ctx->opcode, 11, 5);
op1 = MASK_SPECIAL2(ctx->opcode);
gen_arith(ctx, op1, rd, rs, rt);
}
break;
case OPC_MXU__POOL00:
decode_opc_mxu__pool00(env, ctx);
break;