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target/arm: Introduce neon_full_reg_offset
This function makes it clear that we're talking about the whole register, and not the 32-bit piece at index 0. This fixes a bug when running on a big-endian host. Backports 015ee81a4c06b644969f621fd9965cc6372b879e
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2f0940677e
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@ -76,7 +76,7 @@ neon_element_offset(int reg, int element, MemOp size)
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ofs ^= 8 - element_size;
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}
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#endif
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return neon_reg_offset(reg, 0) + ofs;
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return neon_full_reg_offset(reg) + ofs;
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}
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static void neon_load_element(DisasContext *s, TCGv_i32 var, int reg, int ele, MemOp mop)
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@ -600,12 +600,12 @@ static bool trans_VLD_all_lanes(DisasContext *s, arg_VLD_all_lanes *a)
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* We cannot write 16 bytes at once because the
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* destination is unaligned.
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*/
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tcg_gen_gvec_dup_i32(tcg_ctx, size, neon_reg_offset(vd, 0),
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tcg_gen_gvec_dup_i32(tcg_ctx, size, neon_full_reg_offset(vd),
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8, 8, tmp);
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tcg_gen_gvec_mov(tcg_ctx, 0, neon_reg_offset(vd + 1, 0),
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neon_reg_offset(vd, 0), 8, 8);
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tcg_gen_gvec_mov(tcg_ctx, 0, neon_full_reg_offset(vd + 1),
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neon_full_reg_offset(vd), 8, 8);
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} else {
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tcg_gen_gvec_dup_i32(tcg_ctx, size, neon_reg_offset(vd, 0),
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tcg_gen_gvec_dup_i32(tcg_ctx, size, neon_full_reg_offset(vd),
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vec_size, vec_size, tmp);
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}
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tcg_gen_addi_i32(tcg_ctx, addr, addr, 1 << size);
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@ -707,9 +707,9 @@ static bool trans_VLDST_single(DisasContext *s, arg_VLDST_single *a)
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static bool do_3same(DisasContext *s, arg_3same *a, GVecGen3Fn fn)
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{
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int vec_size = a->q ? 16 : 8;
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int rd_ofs = neon_reg_offset(a->vd, 0);
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int rn_ofs = neon_reg_offset(a->vn, 0);
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int rm_ofs = neon_reg_offset(a->vm, 0);
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int rd_ofs = neon_full_reg_offset(a->vd);
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int rn_ofs = neon_full_reg_offset(a->vn);
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int rm_ofs = neon_full_reg_offset(a->vm);
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TCGContext *tcg_ctx = s->uc->tcg_ctx;
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if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
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@ -1198,8 +1198,8 @@ static bool do_vector_2sh(DisasContext *s, arg_2reg_shift *a, GVecGen2iFn *fn)
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/* Handle a 2-reg-shift insn which can be vectorized. */
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TCGContext *tcg_ctx = s->uc->tcg_ctx;
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int vec_size = a->q ? 16 : 8;
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int rd_ofs = neon_reg_offset(a->vd, 0);
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int rm_ofs = neon_reg_offset(a->vm, 0);
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int rd_ofs = neon_full_reg_offset(a->vd);
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int rm_ofs = neon_full_reg_offset(a->vm);
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if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
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return false;
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@ -1647,8 +1647,8 @@ static bool do_fp_2sh(DisasContext *s, arg_2reg_shift *a,
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/* FP operations in 2-reg-and-shift group */
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TCGContext *tcg_ctx = s->uc->tcg_ctx;
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int vec_size = a->q ? 16 : 8;
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int rd_ofs = neon_reg_offset(a->vd, 0);
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int rm_ofs = neon_reg_offset(a->vm, 0);
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int rd_ofs = neon_full_reg_offset(a->vd);
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int rm_ofs = neon_full_reg_offset(a->vm);
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TCGv_ptr fpst;
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if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
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@ -1784,7 +1784,7 @@ static bool do_1reg_imm(DisasContext *s, arg_1reg_imm *a,
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return true;
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}
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reg_ofs = neon_reg_offset(a->vd, 0);
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reg_ofs = neon_full_reg_offset(a->vd);
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vec_size = a->q ? 16 : 8;
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imm = asimd_imm_const(a->imm, a->cmode, a->op);
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@ -2332,9 +2332,9 @@ static bool trans_VMULL_P_3d(DisasContext *s, arg_3diff *a)
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return true;
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}
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tcg_gen_gvec_3_ool(tcg_ctx, neon_reg_offset(a->vd, 0),
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neon_reg_offset(a->vn, 0),
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neon_reg_offset(a->vm, 0),
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tcg_gen_gvec_3_ool(tcg_ctx, neon_full_reg_offset(a->vd),
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neon_full_reg_offset(a->vn),
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neon_full_reg_offset(a->vm),
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16, 16, 0, fn_gvec);
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return true;
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}
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@ -2480,8 +2480,8 @@ static bool do_2scalar_fp_vec(DisasContext *s, arg_2scalar *a,
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/* Two registers and a scalar, using gvec */
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TCGContext *tcg_ctx = s->uc->tcg_ctx;
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int vec_size = a->q ? 16 : 8;
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int rd_ofs = neon_reg_offset(a->vd, 0);
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int rn_ofs = neon_reg_offset(a->vn, 0);
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int rd_ofs = neon_full_reg_offset(a->vd);
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int rn_ofs = neon_full_reg_offset(a->vn);
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int rm_ofs;
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int idx;
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TCGv_ptr fpstatus;
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@ -2512,7 +2512,7 @@ static bool do_2scalar_fp_vec(DisasContext *s, arg_2scalar *a,
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/* a->vm is M:Vm, which encodes both register and index */
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idx = extract32(a->vm, a->size + 2, 2);
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a->vm = extract32(a->vm, 0, a->size + 2);
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rm_ofs = neon_reg_offset(a->vm, 0);
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rm_ofs = neon_full_reg_offset(a->vm);
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fpstatus = fpstatus_ptr(tcg_ctx, a->size == 1 ? FPST_STD_F16 : FPST_STD);
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tcg_gen_gvec_3_ptr(tcg_ctx, rd_ofs, rn_ofs, rm_ofs, fpstatus,
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@ -2965,7 +2965,7 @@ static bool trans_VDUP_scalar(DisasContext *s, arg_VDUP_scalar *a)
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return true;
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}
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tcg_gen_gvec_dup_mem(tcg_ctx, a->size, neon_reg_offset(a->vd, 0),
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tcg_gen_gvec_dup_mem(tcg_ctx, a->size, neon_full_reg_offset(a->vd),
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neon_element_offset(a->vm, a->index, a->size),
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a->q ? 16 : 8, a->q ? 16 : 8);
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return true;
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@ -3462,8 +3462,8 @@ static bool do_2misc_vec(DisasContext *s, arg_2misc *a, GVecGen2Fn *fn)
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{
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TCGContext *tcg_ctx = s->uc->tcg_ctx;
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int vec_size = a->q ? 16 : 8;
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int rd_ofs = neon_reg_offset(a->vd, 0);
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int rm_ofs = neon_reg_offset(a->vm, 0);
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int rd_ofs = neon_full_reg_offset(a->vd);
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int rm_ofs = neon_full_reg_offset(a->vm);
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if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
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return false;
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@ -662,7 +662,7 @@ static bool trans_VDUP(DisasContext *s, arg_VDUP *a)
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}
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tmp = load_reg(s, a->rt);
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tcg_gen_gvec_dup_i32(tcg_ctx, size, neon_reg_offset(a->vn, 0),
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tcg_gen_gvec_dup_i32(tcg_ctx, size, neon_full_reg_offset(a->vn),
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vec_size, vec_size, tmp);
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tcg_temp_free_i32(tcg_ctx, tmp);
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@ -1138,6 +1138,14 @@ static inline void gen_hlt(DisasContext *s, int imm)
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unallocated_encoding(s);
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}
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/*
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* Return the offset of a "full" NEON Dreg.
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*/
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static long neon_full_reg_offset(unsigned reg)
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{
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return offsetof(CPUARMState, vfp.zregs[reg >> 1].d[reg & 1]);
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}
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static inline long vfp_reg_offset(bool dp, unsigned reg)
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{
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if (dp) {
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