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target/arm: Introduce neon_full_reg_offset

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This function makes it clear that we're talking about the whole
register, and not the 32-bit piece at index 0. This fixes a bug
when running on a big-endian host.

Backports 015ee81a4c06b644969f621fd9965cc6372b879e
This commit is contained in:
Richard Henderson 2021-03-02 11:50:30 -05:00 committed by Lioncash
parent 2f0940677e
commit 8a20537e7f
3 changed files with 31 additions and 23 deletions
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44
qemu/target/arm/translate-neon.inc.c
View file

@ -76,7 +76,7 @@ neon_element_offset(int reg, int element, MemOp size)
ofs ^= 8 - element_size; ofs ^= 8 - element_size;
} }
#endif #endif
return neon_reg_offset(reg, 0) + ofs; return neon_full_reg_offset(reg) + ofs;
} }
static void neon_load_element(DisasContext *s, TCGv_i32 var, int reg, int ele, MemOp mop) static void neon_load_element(DisasContext *s, TCGv_i32 var, int reg, int ele, MemOp mop)
@ -600,12 +600,12 @@ static bool trans_VLD_all_lanes(DisasContext *s, arg_VLD_all_lanes *a)
* We cannot write 16 bytes at once because the * We cannot write 16 bytes at once because the
* destination is unaligned. * destination is unaligned.
*/ */
tcg_gen_gvec_dup_i32(tcg_ctx, size, neon_reg_offset(vd, 0), tcg_gen_gvec_dup_i32(tcg_ctx, size, neon_full_reg_offset(vd),
8, 8, tmp); 8, 8, tmp);
tcg_gen_gvec_mov(tcg_ctx, 0, neon_reg_offset(vd + 1, 0), tcg_gen_gvec_mov(tcg_ctx, 0, neon_full_reg_offset(vd + 1),
neon_reg_offset(vd, 0), 8, 8); neon_full_reg_offset(vd), 8, 8);
} else { } else {
tcg_gen_gvec_dup_i32(tcg_ctx, size, neon_reg_offset(vd, 0), tcg_gen_gvec_dup_i32(tcg_ctx, size, neon_full_reg_offset(vd),
vec_size, vec_size, tmp); vec_size, vec_size, tmp);
} }
tcg_gen_addi_i32(tcg_ctx, addr, addr, 1 << size); tcg_gen_addi_i32(tcg_ctx, addr, addr, 1 << size);
@ -707,9 +707,9 @@ static bool trans_VLDST_single(DisasContext *s, arg_VLDST_single *a)
static bool do_3same(DisasContext *s, arg_3same *a, GVecGen3Fn fn) static bool do_3same(DisasContext *s, arg_3same *a, GVecGen3Fn fn)
{ {
int vec_size = a->q ? 16 : 8; int vec_size = a->q ? 16 : 8;
int rd_ofs = neon_reg_offset(a->vd, 0); int rd_ofs = neon_full_reg_offset(a->vd);
int rn_ofs = neon_reg_offset(a->vn, 0); int rn_ofs = neon_full_reg_offset(a->vn);
int rm_ofs = neon_reg_offset(a->vm, 0); int rm_ofs = neon_full_reg_offset(a->vm);
TCGContext *tcg_ctx = s->uc->tcg_ctx; TCGContext *tcg_ctx = s->uc->tcg_ctx;
if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
@ -1198,8 +1198,8 @@ static bool do_vector_2sh(DisasContext *s, arg_2reg_shift *a, GVecGen2iFn *fn)
/* Handle a 2-reg-shift insn which can be vectorized. */ /* Handle a 2-reg-shift insn which can be vectorized. */
TCGContext *tcg_ctx = s->uc->tcg_ctx; TCGContext *tcg_ctx = s->uc->tcg_ctx;
int vec_size = a->q ? 16 : 8; int vec_size = a->q ? 16 : 8;
int rd_ofs = neon_reg_offset(a->vd, 0); int rd_ofs = neon_full_reg_offset(a->vd);
int rm_ofs = neon_reg_offset(a->vm, 0); int rm_ofs = neon_full_reg_offset(a->vm);
if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
return false; return false;
@ -1647,8 +1647,8 @@ static bool do_fp_2sh(DisasContext *s, arg_2reg_shift *a,
/* FP operations in 2-reg-and-shift group */ /* FP operations in 2-reg-and-shift group */
TCGContext *tcg_ctx = s->uc->tcg_ctx; TCGContext *tcg_ctx = s->uc->tcg_ctx;
int vec_size = a->q ? 16 : 8; int vec_size = a->q ? 16 : 8;
int rd_ofs = neon_reg_offset(a->vd, 0); int rd_ofs = neon_full_reg_offset(a->vd);
int rm_ofs = neon_reg_offset(a->vm, 0); int rm_ofs = neon_full_reg_offset(a->vm);
TCGv_ptr fpst; TCGv_ptr fpst;
if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
@ -1784,7 +1784,7 @@ static bool do_1reg_imm(DisasContext *s, arg_1reg_imm *a,
return true; return true;
} }
reg_ofs = neon_reg_offset(a->vd, 0); reg_ofs = neon_full_reg_offset(a->vd);
vec_size = a->q ? 16 : 8; vec_size = a->q ? 16 : 8;
imm = asimd_imm_const(a->imm, a->cmode, a->op); imm = asimd_imm_const(a->imm, a->cmode, a->op);
@ -2332,9 +2332,9 @@ static bool trans_VMULL_P_3d(DisasContext *s, arg_3diff *a)
return true; return true;
} }
tcg_gen_gvec_3_ool(tcg_ctx, neon_reg_offset(a->vd, 0), tcg_gen_gvec_3_ool(tcg_ctx, neon_full_reg_offset(a->vd),
neon_reg_offset(a->vn, 0), neon_full_reg_offset(a->vn),
neon_reg_offset(a->vm, 0), neon_full_reg_offset(a->vm),
16, 16, 0, fn_gvec); 16, 16, 0, fn_gvec);
return true; return true;
} }
@ -2480,8 +2480,8 @@ static bool do_2scalar_fp_vec(DisasContext *s, arg_2scalar *a,
/* Two registers and a scalar, using gvec */ /* Two registers and a scalar, using gvec */
TCGContext *tcg_ctx = s->uc->tcg_ctx; TCGContext *tcg_ctx = s->uc->tcg_ctx;
int vec_size = a->q ? 16 : 8; int vec_size = a->q ? 16 : 8;
int rd_ofs = neon_reg_offset(a->vd, 0); int rd_ofs = neon_full_reg_offset(a->vd);
int rn_ofs = neon_reg_offset(a->vn, 0); int rn_ofs = neon_full_reg_offset(a->vn);
int rm_ofs; int rm_ofs;
int idx; int idx;
TCGv_ptr fpstatus; TCGv_ptr fpstatus;
@ -2512,7 +2512,7 @@ static bool do_2scalar_fp_vec(DisasContext *s, arg_2scalar *a,
/* a->vm is M:Vm, which encodes both register and index */ /* a->vm is M:Vm, which encodes both register and index */
idx = extract32(a->vm, a->size + 2, 2); idx = extract32(a->vm, a->size + 2, 2);
a->vm = extract32(a->vm, 0, a->size + 2); a->vm = extract32(a->vm, 0, a->size + 2);
rm_ofs = neon_reg_offset(a->vm, 0); rm_ofs = neon_full_reg_offset(a->vm);
fpstatus = fpstatus_ptr(tcg_ctx, a->size == 1 ? FPST_STD_F16 : FPST_STD); fpstatus = fpstatus_ptr(tcg_ctx, a->size == 1 ? FPST_STD_F16 : FPST_STD);
tcg_gen_gvec_3_ptr(tcg_ctx, rd_ofs, rn_ofs, rm_ofs, fpstatus, tcg_gen_gvec_3_ptr(tcg_ctx, rd_ofs, rn_ofs, rm_ofs, fpstatus,
@ -2965,7 +2965,7 @@ static bool trans_VDUP_scalar(DisasContext *s, arg_VDUP_scalar *a)
return true; return true;
} }
tcg_gen_gvec_dup_mem(tcg_ctx, a->size, neon_reg_offset(a->vd, 0), tcg_gen_gvec_dup_mem(tcg_ctx, a->size, neon_full_reg_offset(a->vd),
neon_element_offset(a->vm, a->index, a->size), neon_element_offset(a->vm, a->index, a->size),
a->q ? 16 : 8, a->q ? 16 : 8); a->q ? 16 : 8, a->q ? 16 : 8);
return true; return true;
@ -3462,8 +3462,8 @@ static bool do_2misc_vec(DisasContext *s, arg_2misc *a, GVecGen2Fn *fn)
{ {
TCGContext *tcg_ctx = s->uc->tcg_ctx; TCGContext *tcg_ctx = s->uc->tcg_ctx;
int vec_size = a->q ? 16 : 8; int vec_size = a->q ? 16 : 8;
int rd_ofs = neon_reg_offset(a->vd, 0); int rd_ofs = neon_full_reg_offset(a->vd);
int rm_ofs = neon_reg_offset(a->vm, 0); int rm_ofs = neon_full_reg_offset(a->vm);
if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
return false; return false;

2
qemu/target/arm/translate-vfp.inc.c
View file

@ -662,7 +662,7 @@ static bool trans_VDUP(DisasContext *s, arg_VDUP *a)
} }
tmp = load_reg(s, a->rt); tmp = load_reg(s, a->rt);
tcg_gen_gvec_dup_i32(tcg_ctx, size, neon_reg_offset(a->vn, 0), tcg_gen_gvec_dup_i32(tcg_ctx, size, neon_full_reg_offset(a->vn),
vec_size, vec_size, tmp); vec_size, vec_size, tmp);
tcg_temp_free_i32(tcg_ctx, tmp); tcg_temp_free_i32(tcg_ctx, tmp);

8
qemu/target/arm/translate.c
View file

@ -1138,6 +1138,14 @@ static inline void gen_hlt(DisasContext *s, int imm)
unallocated_encoding(s); unallocated_encoding(s);
} }
/*
* Return the offset of a "full" NEON Dreg.
*/
static long neon_full_reg_offset(unsigned reg)
{
return offsetof(CPUARMState, vfp.zregs[reg >> 1].d[reg & 1]);
}
static inline long vfp_reg_offset(bool dp, unsigned reg) static inline long vfp_reg_offset(bool dp, unsigned reg)
{ {
if (dp) { if (dp) {