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arm/translate-a64: add FP16 FCMxx (zero) to simd_two_reg_misc_fp16
I re-use the existing handle_2misc_fcmp_zero handler and tweak it slightly to deal with the half-precision case. Backports commit 7d4dd1a73a023f75c893623710e43743501b318e from qemu
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@ -7954,14 +7954,14 @@ static void handle_2misc_fcmp_zero(DisasContext *s, int opcode,
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int size, int rn, int rd)
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{
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TCGContext *tcg_ctx = s->uc->tcg_ctx;
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bool is_double = (size == 3);
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bool is_double = (size == MO_64);
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TCGv_ptr fpst;
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if (!fp_access_check(s)) {
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return;
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}
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fpst = get_fpstatus_ptr(tcg_ctx, false);
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fpst = get_fpstatus_ptr(tcg_ctx, size == MO_16);
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if (is_double) {
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TCGv_i64 tcg_op = tcg_temp_new_i64(tcg_ctx);
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@ -8014,34 +8014,57 @@ static void handle_2misc_fcmp_zero(DisasContext *s, int opcode,
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bool swap = false;
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int pass, maxpasses;
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switch (opcode) {
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case 0x2e: /* FCMLT (zero) */
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swap = true;
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/* fall through */
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case 0x2c: /* FCMGT (zero) */
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genfn = gen_helper_neon_cgt_f32;
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break;
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case 0x2d: /* FCMEQ (zero) */
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genfn = gen_helper_neon_ceq_f32;
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break;
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case 0x6d: /* FCMLE (zero) */
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swap = true;
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/* fall through */
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case 0x6c: /* FCMGE (zero) */
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genfn = gen_helper_neon_cge_f32;
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break;
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default:
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g_assert_not_reached();
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if (size == MO_16) {
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switch (opcode) {
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case 0x2e: /* FCMLT (zero) */
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swap = true;
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/* fall through */
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case 0x2c: /* FCMGT (zero) */
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genfn = gen_helper_advsimd_cgt_f16;
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break;
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case 0x2d: /* FCMEQ (zero) */
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genfn = gen_helper_advsimd_ceq_f16;
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break;
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case 0x6d: /* FCMLE (zero) */
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swap = true;
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/* fall through */
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case 0x6c: /* FCMGE (zero) */
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genfn = gen_helper_advsimd_cge_f16;
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break;
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default:
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g_assert_not_reached();
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}
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} else {
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switch (opcode) {
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case 0x2e: /* FCMLT (zero) */
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swap = true;
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/* fall through */
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case 0x2c: /* FCMGT (zero) */
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genfn = gen_helper_neon_cgt_f32;
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break;
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case 0x2d: /* FCMEQ (zero) */
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genfn = gen_helper_neon_ceq_f32;
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break;
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case 0x6d: /* FCMLE (zero) */
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swap = true;
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/* fall through */
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case 0x6c: /* FCMGE (zero) */
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genfn = gen_helper_neon_cge_f32;
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break;
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default:
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g_assert_not_reached();
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}
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}
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if (is_scalar) {
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maxpasses = 1;
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} else {
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maxpasses = is_q ? 4 : 2;
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int vector_size = 8 << is_q;
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maxpasses = vector_size >> size;
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}
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for (pass = 0; pass < maxpasses; pass++) {
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read_vec_element_i32(s, tcg_op, rn, pass, MO_32);
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read_vec_element_i32(s, tcg_op, rn, pass, size);
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if (swap) {
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genfn(tcg_ctx, tcg_res, tcg_zero, tcg_op, fpst);
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} else {
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@ -8050,7 +8073,7 @@ static void handle_2misc_fcmp_zero(DisasContext *s, int opcode,
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if (is_scalar) {
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write_fp_sreg(s, rd, tcg_res);
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} else {
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write_vec_element_i32(s, tcg_res, rd, pass, MO_32);
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write_vec_element_i32(s, tcg_res, rd, pass, size);
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}
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}
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tcg_temp_free_i32(tcg_ctx, tcg_res);
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@ -11366,7 +11389,18 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
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fpop = deposit32(opcode, 5, 1, a);
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fpop = deposit32(fpop, 6, 1, u);
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rd = extract32(insn, 0, 5);
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rn = extract32(insn, 5, 5);
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switch (fpop) {
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break;
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case 0x2c: /* FCMGT (zero) */
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case 0x2d: /* FCMEQ (zero) */
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case 0x2e: /* FCMLT (zero) */
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case 0x6c: /* FCMGE (zero) */
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case 0x6d: /* FCMLE (zero) */
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handle_2misc_fcmp_zero(s, fpop, is_scalar, 0, is_q, MO_16, rn, rd);
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return;
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case 0x18: /* FRINTN */
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need_rmode = true;
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only_in_vector = true;
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