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target/mips: Fix pre-nanoMIPS MT ASE instructions availability control

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Use bits from configuration registers for availability control
of MT ASE instructions, rather than only ISA_MT bit in insn_flags.
This is done by adding a field in hflags for MT bit, and adding
functions check_mt() and check_cp0_mt().

Backports commit 9affc1c59279f482ff145e0371926f79b6448e3e from qemu
This commit is contained in:
Aleksandar Rikalo 2018-08-27 05:36:30 -04:00 committed by Lioncash
parent 93f7cd2307
commit 8c0248696a
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 38 additions and 8 deletions
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46
qemu/target/mips/translate.c
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@ -1933,6 +1933,36 @@ static inline void check_xnp(DisasContext *ctx)
}
}
/*
* This code generates a "reserved instruction" exception if the
* Config3 MT bit is NOT set.
*/
static inline void check_mt(DisasContext *ctx)
{
if (unlikely(!(ctx->CP0_Config3 & (1 << CP0C3_MT)))) {
generate_exception_end(ctx, EXCP_RI);
}
}
#ifndef CONFIG_USER_ONLY
/*
* This code generates a "coprocessor unusable" exception if CP0 is not
* available, and, if that is not the case, generates a "reserved instruction"
* exception if the Config5 MT bit is NOT set. This is needed for availability
* control of some of MT ASE instructions.
*/
static inline void check_cp0_mt(DisasContext *ctx)
{
if (unlikely(!(ctx->hflags & MIPS_HFLAG_CP0))) {
generate_exception_err(ctx, EXCP_CpU, 0);
} else {
if (unlikely(!(ctx->CP0_Config3 & (1 << CP0C3_MT)))) {
generate_exception_err(ctx, EXCP_RI, 0);
}
}
}
#endif
/* Define small wrappers for gen_load_fpr* so that we have a uniform
calling interface for 32 and 64-bit FPRs. No sense in changing
@ -8667,7 +8697,7 @@ static void gen_cp0 (CPUMIPSState *env, DisasContext *ctx, uint32_t opc, int rt,
opn = "mthc0";
break;
case OPC_MFTR:
check_insn(ctx, ASE_MT);
check_cp0_enabled(ctx);
if (rd == 0) {
/* Treat as NOP. */
return;
@ -8677,7 +8707,7 @@ static void gen_cp0 (CPUMIPSState *env, DisasContext *ctx, uint32_t opc, int rt,
opn = "mftr";
break;
case OPC_MTTR:
check_insn(ctx, ASE_MT);
check_cp0_enabled(ctx);
gen_mttr(env, ctx, rd, rt, (ctx->opcode >> 5) & 1,
ctx->opcode & 0x7, (ctx->opcode >> 4) & 1);
opn = "mttr";
@ -22097,7 +22127,7 @@ static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx)
gen_rdhwr(ctx, rt, rd, extract32(ctx->opcode, 6, 3));
break;
case OPC_FORK:
check_insn(ctx, ASE_MT);
check_mt(ctx);
{
TCGv t0 = tcg_temp_new(tcg_ctx);
TCGv t1 = tcg_temp_new(tcg_ctx);
@ -22110,7 +22140,7 @@ static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx)
}
break;
case OPC_YIELD:
check_insn(ctx, ASE_MT);
check_mt(ctx);
{
TCGv t0 = tcg_temp_new(tcg_ctx);
@ -23438,22 +23468,22 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx, bool *insn_need_pat
op2 = MASK_MFMC0(ctx->opcode);
switch (op2) {
case OPC_DMT:
check_insn(ctx, ASE_MT);
check_cp0_mt(ctx);
gen_helper_dmt(tcg_ctx, t0);
gen_store_gpr(tcg_ctx, t0, rt);
break;
case OPC_EMT:
check_insn(ctx, ASE_MT);
check_cp0_mt(ctx);
gen_helper_emt(tcg_ctx, t0);
gen_store_gpr(tcg_ctx, t0, rt);
break;
case OPC_DVPE:
check_insn(ctx, ASE_MT);
check_cp0_mt(ctx);
gen_helper_dvpe(tcg_ctx, t0, tcg_ctx->cpu_env);
gen_store_gpr(tcg_ctx, t0, rt);
break;
case OPC_EVPE:
check_insn(ctx, ASE_MT);
check_cp0_mt(ctx);
gen_helper_evpe(tcg_ctx, t0, tcg_ctx->cpu_env);
gen_store_gpr(tcg_ctx, t0, rt);
break;