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target/arm: Add state field, feature bit and migration for v8M secure state
As the first step in implementing ARM v8M's security extension: * add a new feature bit ARM_FEATURE_M_SECURITY * add the CPU state field that indicates whether the CPU is currently in the secure state * add a migration subsection for this new state (we will add the Secure copies of banked register state to this subsection in later patches) * add a #define for the one new-in-v8M exception type * make the CPU debug log print S/NS status Backports commit 1e577cc7cffd3de14dbd321de5c3ef191c6ab07f from qemu
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@ -12509,6 +12509,11 @@ void arm_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
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if (arm_feature(env, ARM_FEATURE_M)) {
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uint32_t xpsr = xpsr_read(env);
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const char *mode;
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const char *ns_status = "";
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if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
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ns_status = env->v7m.secure ? "S " : "NS ";
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}
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if (xpsr & XPSR_EXCP) {
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mode = "handler";
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@ -12520,13 +12525,14 @@ void arm_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
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}
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}
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cpu_fprintf(f, "XPSR=%08x %c%c%c%c %c %s\n",
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cpu_fprintf(f, "XPSR=%08x %c%c%c%c %c %s%s\n",
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xpsr,
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xpsr & XPSR_N ? 'N' : '-',
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xpsr & XPSR_Z ? 'Z' : '-',
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xpsr & XPSR_C ? 'C' : '-',
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xpsr & XPSR_V ? 'V' : '-',
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xpsr & XPSR_T ? 'T' : 'A',
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ns_status,
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mode);
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} else {
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uint32_t psr = cpsr_read(env);
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