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target/arm: Add state field, feature bit and migration for v8M secure state

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As the first step in implementing ARM v8M's security extension:
* add a new feature bit ARM_FEATURE_M_SECURITY
* add the CPU state field that indicates whether the CPU is
currently in the secure state
* add a migration subsection for this new state
(we will add the Secure copies of banked register state
to this subsection in later patches)
* add a #define for the one new-in-v8M exception type
* make the CPU debug log print S/NS status

Backports commit 1e577cc7cffd3de14dbd321de5c3ef191c6ab07f from qemu
This commit is contained in:
Peter Maydell 2018-03-04 20:50:02 -05:00 committed by Lioncash
parent 829a34ec55
commit 8ce42ad30c
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 7 additions and 1 deletions
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8
qemu/target/arm/translate.c
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@ -12509,6 +12509,11 @@ void arm_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
if (arm_feature(env, ARM_FEATURE_M)) { if (arm_feature(env, ARM_FEATURE_M)) {
uint32_t xpsr = xpsr_read(env); uint32_t xpsr = xpsr_read(env);
const char *mode; const char *mode;
const char *ns_status = "";
if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
ns_status = env->v7m.secure ? "S " : "NS ";
}
if (xpsr & XPSR_EXCP) { if (xpsr & XPSR_EXCP) {
mode = "handler"; mode = "handler";
@ -12520,13 +12525,14 @@ void arm_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
} }
} }
cpu_fprintf(f, "XPSR=%08x %c%c%c%c %c %s\n", cpu_fprintf(f, "XPSR=%08x %c%c%c%c %c %s%s\n",
xpsr, xpsr,
xpsr & XPSR_N ? 'N' : '-', xpsr & XPSR_N ? 'N' : '-',
xpsr & XPSR_Z ? 'Z' : '-', xpsr & XPSR_Z ? 'Z' : '-',
xpsr & XPSR_C ? 'C' : '-', xpsr & XPSR_C ? 'C' : '-',
xpsr & XPSR_V ? 'V' : '-', xpsr & XPSR_V ? 'V' : '-',
xpsr & XPSR_T ? 'T' : 'A', xpsr & XPSR_T ? 'T' : 'A',
ns_status,
mode); mode);
} else { } else {
uint32_t psr = cpsr_read(env); uint32_t psr = cpsr_read(env);