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https://github.com/yuzu-emu/unicorn.git
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target/riscv: Convert quadrant 0 of RVXC insns to decodetree
This commit is contained in:
parent
67164f2b29
commit
8d294a7897
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@ -5411,6 +5411,7 @@ riscv_symbols = (
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'cpu_riscv_set_fflags',
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'csr_read_helper',
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'csr_write_helper',
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'decode_insn16',
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'decode_insn32',
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'do_raise_exception_err',
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'gen_helper_tlb_flush',
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@ -3332,6 +3332,7 @@
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#define cpu_riscv_set_fflags cpu_riscv_set_fflags_riscv32
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#define csr_read_helper csr_read_helper_riscv32
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#define csr_write_helper csr_write_helper_riscv32
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#define decode_insn16 decode_insn16_riscv32
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#define decode_insn32 decode_insn32_riscv32
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#define do_raise_exception_err do_raise_exception_err_riscv32
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#define gen_helper_tlb_flush gen_helper_tlb_flush_riscv32
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@ -3332,6 +3332,7 @@
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#define cpu_riscv_set_fflags cpu_riscv_set_fflags_riscv64
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#define csr_read_helper csr_read_helper_riscv64
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#define csr_write_helper csr_write_helper_riscv64
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#define decode_insn16 decode_insn16_riscv64
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#define decode_insn32 decode_insn32_riscv64
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#define do_raise_exception_err do_raise_exception_err_riscv64
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#define gen_helper_tlb_flush gen_helper_tlb_flush_riscv64
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@ -11,4 +11,12 @@ target/riscv/decode_insn32.inc.c: $(decode32-y) $(DECODETREE)
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$(PYTHON) $(DECODETREE) -o $@ --decode decode_insn32 $(decode32-y), \
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"GEN", $(TARGET_DIR)$@)
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target/riscv/translate.o: target/riscv/decode_insn32.inc.c
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target/riscv/decode_insn16.inc.c: \
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$(SRC_PATH)/target/riscv/insn16.decode $(DECODETREE)
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$(call quiet-command, \
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$(PYTHON) $(DECODETREE) -o $@ --decode decode_insn16 --insnwidth 16 $<, \
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"GEN", $(TARGET_DIR)$@)
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target/riscv/translate.o: target/riscv/decode_insn32.inc.c \
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target/riscv/decode_insn16.inc.c
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55
qemu/target/riscv/insn16.decode
Normal file
55
qemu/target/riscv/insn16.decode
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@ -0,0 +1,55 @@
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#
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# RISC-V translation routines for the RVXI Base Integer Instruction Set.
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#
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# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
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# Bastian Koppelmann, kbastian@mail.uni-paderborn.de
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#
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# This program is free software; you can redistribute it and/or modify it
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# under the terms and conditions of the GNU General Public License,
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# version 2 or later, as published by the Free Software Foundation.
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#
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# This program is distributed in the hope it will be useful, but WITHOUT
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# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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# more details.
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#
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# You should have received a copy of the GNU General Public License along with
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# this program. If not, see <http://www.gnu.org/licenses/>.
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# Fields:
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%rd 7:5
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%rs1_3 7:3 !function=ex_rvc_register
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%rs2_3 2:3 !function=ex_rvc_register
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# Immediates:
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%nzuimm_ciw 7:4 11:2 5:1 6:1 !function=ex_shift_2
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%uimm_cl_d 5:2 10:3 !function=ex_shift_3
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%uimm_cl_w 5:1 10:3 6:1 !function=ex_shift_2
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# Argument sets:
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&cl rs1 rd
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&cl_dw uimm rs1 rd
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&ciw nzuimm rd
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&cs rs1 rs2
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&cs_dw uimm rs1 rs2
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# Formats 16:
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@ciw ... ........ ... .. &ciw nzuimm=%nzuimm_ciw rd=%rs2_3
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@cl_d ... ... ... .. ... .. &cl_dw uimm=%uimm_cl_d rs1=%rs1_3 rd=%rs2_3
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@cl_w ... ... ... .. ... .. &cl_dw uimm=%uimm_cl_w rs1=%rs1_3 rd=%rs2_3
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@cl ... ... ... .. ... .. &cl rs1=%rs1_3 rd=%rs2_3
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@cs ... ... ... .. ... .. &cs rs1=%rs1_3 rs2=%rs2_3
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@cs_d ... ... ... .. ... .. &cs_dw uimm=%uimm_cl_d rs1=%rs1_3 rs2=%rs2_3
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@cs_w ... ... ... .. ... .. &cs_dw uimm=%uimm_cl_w rs1=%rs1_3 rs2=%rs2_3
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# *** RV64C Standard Extension (Quadrant 0) ***
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c_addi4spn 000 ........ ... 00 @ciw
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c_fld 001 ... ... .. ... 00 @cl_d
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c_lw 010 ... ... .. ... 00 @cl_w
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c_flw_ld 011 --- ... -- ... 00 @cl #Note: Must parse uimm manually
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c_fsd 101 ... ... .. ... 00 @cs_d
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c_sw 110 ... ... .. ... 00 @cs_w
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c_fsw_sd 111 --- ... -- ... 00 @cs #Note: Must parse uimm manually
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75
qemu/target/riscv/insn_trans/trans_rvc.inc.c
Normal file
75
qemu/target/riscv/insn_trans/trans_rvc.inc.c
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@ -0,0 +1,75 @@
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/*
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* RISC-V translation routines for the RVC Compressed Instruction Set.
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*
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* Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
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* Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
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* Bastian Koppelmann, kbastian@mail.uni-paderborn.de
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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static bool trans_c_addi4spn(DisasContext *ctx, arg_c_addi4spn *a)
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{
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if (a->nzuimm == 0) {
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/* Reserved in ISA */
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return false;
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}
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arg_addi arg = { .rd = a->rd, .rs1 = 2, .imm = a->nzuimm };
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return trans_addi(ctx, &arg);
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}
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static bool trans_c_fld(DisasContext *ctx, arg_c_fld *a)
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{
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arg_fld arg = { .rd = a->rd, .rs1 = a->rs1, .imm = a->uimm };
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return trans_fld(ctx, &arg);
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}
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static bool trans_c_lw(DisasContext *ctx, arg_c_lw *a)
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{
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arg_lw arg = { .rd = a->rd, .rs1 = a->rs1, .imm = a->uimm };
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return trans_lw(ctx, &arg);
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}
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static bool trans_c_flw_ld(DisasContext *ctx, arg_c_flw_ld *a)
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{
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#ifdef TARGET_RISCV32
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/* C.FLW ( RV32FC-only ) */
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return false;
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#else
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/* C.LD ( RV64C/RV128C-only ) */
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return false;
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#endif
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}
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static bool trans_c_fsd(DisasContext *ctx, arg_c_fsd *a)
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{
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arg_fsd arg = { .rs1 = a->rs1, .rs2 = a->rs2, .imm = a->uimm };
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return trans_fsd(ctx, &arg);
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}
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static bool trans_c_sw(DisasContext *ctx, arg_c_sw *a)
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{
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arg_sw arg = { .rs1 = a->rs1, .rs2 = a->rs2, .imm = a->uimm };
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return trans_sw(ctx, &arg);
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}
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static bool trans_c_fsw_sd(DisasContext *ctx, arg_c_fsw_sd *a)
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{
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#ifdef TARGET_RISCV32
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/* C.FSW ( RV32FC-only ) */
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return false;
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#else
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/* C.SD ( RV64C/RV128C-only ) */
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return false;
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#endif
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}
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@ -830,27 +830,6 @@ static void decode_RV32_64C0(DisasContext *ctx)
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uint8_t rs1s = GET_C_RS1S(ctx->opcode);
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switch (funct3) {
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case 0:
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/* illegal */
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if (ctx->opcode == 0) {
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gen_exception_illegal(ctx);
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} else {
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/* C.ADDI4SPN -> addi rd', x2, zimm[9:2]*/
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gen_arith_imm(ctx, OPC_RISC_ADDI, rd_rs2, 2,
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GET_C_ADDI4SPN_IMM(ctx->opcode));
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}
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break;
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case 1:
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/* C.FLD -> fld rd', offset[7:3](rs1')*/
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gen_fp_load(ctx, OPC_RISC_FLD, rd_rs2, rs1s,
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GET_C_LD_IMM(ctx->opcode));
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/* C.LQ(RV128) */
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break;
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case 2:
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/* C.LW -> lw rd', offset[6:2](rs1') */
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gen_load(ctx, OPC_RISC_LW, rd_rs2, rs1s,
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GET_C_LW_IMM(ctx->opcode));
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break;
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case 3:
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#if defined(TARGET_RISCV64)
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/* C.LD(RV64/128) -> ld rd', offset[7:3](rs1')*/
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@ -862,21 +841,6 @@ static void decode_RV32_64C0(DisasContext *ctx)
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GET_C_LW_IMM(ctx->opcode));
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#endif
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break;
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case 4:
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/* reserved */
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gen_exception_illegal(ctx);
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break;
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case 5:
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/* C.FSD(RV32/64) -> fsd rs2', offset[7:3](rs1') */
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gen_fp_store(ctx, OPC_RISC_FSD, rs1s, rd_rs2,
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GET_C_LD_IMM(ctx->opcode));
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/* C.SQ (RV128) */
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break;
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case 6:
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/* C.SW -> sw rs2', offset[6:2](rs1')*/
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gen_store(ctx, OPC_RISC_SW, rs1s, rd_rs2,
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GET_C_LW_IMM(ctx->opcode));
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break;
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case 7:
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#if defined(TARGET_RISCV64)
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/* C.SD (RV64/128) -> sd rs2', offset[7:3](rs1')*/
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@ -1107,6 +1071,8 @@ static void decode_RV32_64C(DisasContext *ctx)
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return imm << amount; \
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}
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EX_SH(1)
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EX_SH(2)
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EX_SH(3)
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EX_SH(12)
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#define REQUIRE_EXT(ctx, ext) do { \
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@ -1115,6 +1081,11 @@ EX_SH(12)
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} \
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} while (0)
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static int ex_rvc_register(int reg)
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{
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return 8 + reg;
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}
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bool decode_insn32(DisasContext *ctx, uint32_t insn);
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/* Include the auto-generated decoder for 32 bit insn */
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#include "decode_insn32.inc.c"
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@ -1126,6 +1097,11 @@ bool decode_insn32(DisasContext *ctx, uint32_t insn);
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#include "insn_trans/trans_rvd.inc.c"
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#include "insn_trans/trans_privileged.inc.c"
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bool decode_insn16(DisasContext *ctx, uint16_t insn);
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/* auto-generated decoder*/
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#include "decode_insn16.inc.c"
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#include "insn_trans/trans_rvc.inc.c"
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static void decode_RV32_64G(DisasContext *ctx)
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{
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int rs1, rd;
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@ -1159,7 +1135,10 @@ static void decode_opc(DisasContext *ctx)
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gen_exception_illegal(ctx);
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} else {
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ctx->pc_succ_insn = ctx->base.pc_next + 2;
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decode_RV32_64C(ctx);
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if (!decode_insn16(ctx, ctx->opcode)) {
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/* fall back to old decoder */
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decode_RV32_64C(ctx);
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}
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}
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} else {
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ctx->pc_succ_insn = ctx->base.pc_next + 4;
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