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target/arm: Don't clear supported PMU events when initializing PMCEID1
A bug was introduced during a respin of: commit 57a4a11b2b281bb548b419ca81bfafb214e4c77a target/arm: Add array for supported PMU events, generate PMCEID[01]_EL0 This patch introduced two calls to get_pmceid() during CPU initialization - one each for PMCEID0 and PMCEID1. In addition to building the register values, get_pmceid() clears an internal array mapping event numbers to their implementations (supported_event_map) before rebuilding it. This is an optimization since much of the logic is shared. However, since it was called twice, the contents of supported_event_map reflect only the events in PMCEID1 (the second call to get_pmceid()). Fix this bug by moving the initialization of PMCEID0 and PMCEID1 back into a single function call, and name it more appropriately since it is doing more than simply generating the contents of the PMCEID[01] registers. Backports commit bf8d09694ccc07487cd73d7562081fdaec3370c8 from qemu
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@ -3337,7 +3337,7 @@
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#define fp_exception_el fp_exception_el_aarch64
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#define fp_exception_el fp_exception_el_aarch64
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#define gen_a64_set_pc_im gen_a64_set_pc_im_aarch64
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#define gen_a64_set_pc_im gen_a64_set_pc_im_aarch64
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#define gen_cmtst_i64 gen_cmtst_i64_aarch64
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#define gen_cmtst_i64 gen_cmtst_i64_aarch64
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#define get_pmceid get_pmceid_aarch64
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#define pmu_init pmu_init_aarch64
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#define helper_advsimd_acge_f16 helper_advsimd_acge_f16_aarch64
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#define helper_advsimd_acge_f16 helper_advsimd_acge_f16_aarch64
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#define helper_advsimd_acgt_f16 helper_advsimd_acgt_f16_aarch64
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#define helper_advsimd_acgt_f16 helper_advsimd_acgt_f16_aarch64
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#define helper_advsimd_add2h helper_advsimd_add2h_aarch64
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#define helper_advsimd_add2h helper_advsimd_add2h_aarch64
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@ -3337,7 +3337,7 @@
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#define fp_exception_el fp_exception_el_aarch64eb
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#define fp_exception_el fp_exception_el_aarch64eb
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#define gen_a64_set_pc_im gen_a64_set_pc_im_aarch64eb
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#define gen_a64_set_pc_im gen_a64_set_pc_im_aarch64eb
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#define gen_cmtst_i64 gen_cmtst_i64_aarch64eb
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#define gen_cmtst_i64 gen_cmtst_i64_aarch64eb
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#define get_pmceid get_pmceid_aarch64eb
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#define pmu_init pmu_init_aarch64eb
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#define helper_advsimd_acge_f16 helper_advsimd_acge_f16_aarch64eb
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#define helper_advsimd_acge_f16 helper_advsimd_acge_f16_aarch64eb
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#define helper_advsimd_acgt_f16 helper_advsimd_acgt_f16_aarch64eb
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#define helper_advsimd_acgt_f16 helper_advsimd_acgt_f16_aarch64eb
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#define helper_advsimd_add2h helper_advsimd_add2h_aarch64eb
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#define helper_advsimd_add2h helper_advsimd_add2h_aarch64eb
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@ -3322,7 +3322,7 @@
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#define cmtst_op cmtst_op_arm
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#define cmtst_op cmtst_op_arm
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#define fp_exception_el fp_exception_el_arm
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#define fp_exception_el fp_exception_el_arm
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#define gen_cmtst_i64 gen_cmtst_i64_arm
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#define gen_cmtst_i64 gen_cmtst_i64_arm
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#define get_pmceid get_pmceid_arm
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#define pmu_init pmu_init_arm
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#define mla_op mla_op_arm
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#define mla_op mla_op_arm
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#define mls_op mls_op_arm
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#define mls_op mls_op_arm
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#define pmccntr_op_start pmccntr_op_start_arm
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#define pmccntr_op_start pmccntr_op_start_arm
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@ -3322,7 +3322,7 @@
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#define cmtst_op cmtst_op_armeb
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#define cmtst_op cmtst_op_armeb
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#define fp_exception_el fp_exception_el_armeb
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#define fp_exception_el fp_exception_el_armeb
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#define gen_cmtst_i64 gen_cmtst_i64_armeb
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#define gen_cmtst_i64 gen_cmtst_i64_armeb
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#define get_pmceid get_pmceid_armeb
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#define pmu_init pmu_init_armeb
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#define mla_op mla_op_armeb
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#define mla_op mla_op_armeb
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#define mls_op mls_op_armeb
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#define mls_op mls_op_armeb
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#define pmccntr_op_start pmccntr_op_start_armeb
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#define pmccntr_op_start pmccntr_op_start_armeb
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@ -3331,7 +3331,7 @@ arm_symbols = (
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'cmtst_op',
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'cmtst_op',
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'fp_exception_el',
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'fp_exception_el',
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'gen_cmtst_i64',
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'gen_cmtst_i64',
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'get_pmceid',
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'pmu_init',
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'mla_op',
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'mla_op',
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'mls_op',
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'mls_op',
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'pmccntr_op_start',
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'pmccntr_op_start',
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@ -3383,7 +3383,7 @@ aarch64_symbols = (
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'fp_exception_el',
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'fp_exception_el',
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'gen_a64_set_pc_im',
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'gen_a64_set_pc_im',
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'gen_cmtst_i64',
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'gen_cmtst_i64',
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'get_pmceid',
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'pmu_init',
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'helper_advsimd_acge_f16',
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'helper_advsimd_acge_f16',
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'helper_advsimd_acgt_f16',
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'helper_advsimd_acgt_f16',
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'helper_advsimd_add2h',
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'helper_advsimd_add2h',
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@ -764,8 +764,7 @@ static int arm_cpu_realizefn(struct uc_struct *uc, DeviceState *dev, Error **err
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}
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}
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if (arm_feature(env, ARM_FEATURE_PMU)) {
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if (arm_feature(env, ARM_FEATURE_PMU)) {
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cpu->pmceid0 = get_pmceid(&cpu->env, 0);
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pmu_init(cpu);
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cpu->pmceid1 = get_pmceid(&cpu->env, 1);
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arm_register_pre_el_change_hook(cpu, &pmu_pre_el_change, 0);
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arm_register_pre_el_change_hook(cpu, &pmu_pre_el_change, 0);
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arm_register_el_change_hook(cpu, &pmu_post_el_change, 0);
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arm_register_el_change_hook(cpu, &pmu_post_el_change, 0);
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@ -964,14 +964,13 @@ void pmu_pre_el_change(ARMCPU *cpu, void *ignored);
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void pmu_post_el_change(ARMCPU *cpu, void *ignored);
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void pmu_post_el_change(ARMCPU *cpu, void *ignored);
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/*
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/*
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* get_pmceid
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* pmu_init
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* @env: CPUARMState
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* @cpu: ARMCPU
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* @which: which PMCEID register to return (0 or 1)
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*
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*
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* Return the PMCEID[01]_EL0 register values corresponding to the counters
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* Initialize the CPU's PMCEID[01]_EL0 registers and associated internal state
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* which are supported given the current configuration
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* for the current configuration
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*/
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*/
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uint64_t get_pmceid(CPUARMState *env, unsigned which);
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void pmu_init(ARMCPU *cpu);
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/* SCTLR bit meanings. Several bits have been reused in newer
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/* SCTLR bit meanings. Several bits have been reused in newer
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* versions of the architecture; in that case we define constants
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* versions of the architecture; in that case we define constants
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@ -952,22 +952,24 @@ static const pm_event pm_events[] = {
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#define UNSUPPORTED_EVENT UINT16_MAX
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#define UNSUPPORTED_EVENT UINT16_MAX
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/*
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/*
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* Called upon initialization to build PMCEID0_EL0 or PMCEID1_EL0 (indicated by
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* Called upon CPU initialization to initialize PMCEID[01]_EL0 and build a map
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* 'which'). We also use it to build a map of ARM event numbers to indices in
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* of ARM event numbers to indices in our pm_events array.
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* our pm_events array.
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*
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*
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* Note: Events in the 0x40XX range are not currently supported.
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* Note: Events in the 0x40XX range are not currently supported.
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*/
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*/
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uint64_t get_pmceid(CPUARMState *env, unsigned which)
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void pmu_init(ARMCPU *cpu)
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{
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{
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uint64_t pmceid = 0;
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unsigned int i;
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unsigned int i;
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assert(which <= 1);
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/*
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* Empty supported_event_map and cpu->pmceid[01] before adding supported
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for (i = 0; i < ARRAY_SIZE(env->supported_event_map); i++) {
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* events to them
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env->supported_event_map[i] = UNSUPPORTED_EVENT;
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*/
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for (i = 0; i < ARRAY_SIZE(cpu->env.supported_event_map); i++) {
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cpu->env.supported_event_map[i] = UNSUPPORTED_EVENT;
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}
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}
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cpu->pmceid0 = 0;
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cpu->pmceid1 = 0;
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for (i = 0; i < ARRAY_SIZE(pm_events); i++) {
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for (i = 0; i < ARRAY_SIZE(pm_events); i++) {
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const pm_event *cnt = &pm_events[i];
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const pm_event *cnt = &pm_events[i];
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@ -975,13 +977,16 @@ uint64_t get_pmceid(CPUARMState *env, unsigned which)
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/* We do not currently support events in the 0x40xx range */
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/* We do not currently support events in the 0x40xx range */
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assert(cnt->number <= 0x3f);
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assert(cnt->number <= 0x3f);
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if ((cnt->number & 0x20) == (which << 6) &&
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if (cnt->supported(&cpu->env)) {
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cnt->supported(env)) {
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cpu->env.supported_event_map[cnt->number] = i;
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pmceid |= (1 << (cnt->number & 0x1f));
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uint64_t event_mask = 1 << (cnt->number & 0x1f);
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env->supported_event_map[cnt->number] = i;
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if (cnt->number & 0x20) {
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cpu->pmceid1 |= event_mask;
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} else {
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cpu->pmceid0 |= event_mask;
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}
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}
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}
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}
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}
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return pmceid;
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}
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}
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/*
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/*
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