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target/mips: fix msa copy_[s|u]_df rd = 0 corner case

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This patch fixes the msa copy_[s|u]_df instruction emulation when
the destination register rd is zero. Without this patch the zero
register would get clobbered, which should never happen because it
is supposed to be hardwired to 0.

Fix this corner case by explicitly checking rd = 0 and effectively
making these instructions emulation no-op in that case.

Backports commit cab4888136a92250fdd401402622824994f7ce0b from qemu
This commit is contained in:
Miodrag Dinic 2018-03-03 22:08:04 -05:00 committed by Lioncash
parent 60703a4f57
commit 8daabd339e
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 6 additions and 2 deletions
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8
qemu/target/mips/translate.c
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@ -18819,10 +18819,14 @@ static void gen_msa_elm_df(CPUMIPSState *env, DisasContext *ctx, uint32_t df,
#endif
switch (MASK_MSA_ELM(ctx->opcode)) {
case OPC_COPY_S_df:
gen_helper_msa_copy_s_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, tn);
if (likely(wd != 0)) {
gen_helper_msa_copy_s_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, tn);
}
break;
case OPC_COPY_U_df:
gen_helper_msa_copy_u_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, tn);
if (likely(wd != 0)) {
gen_helper_msa_copy_u_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, tn);
}
break;
case OPC_INSERT_df:
gen_helper_msa_insert_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, tn);