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tcg: Add field extraction primitives

Browse source 
Adds tcg_gen_extract_* and tcg_gen_sextract_* for extraction of
fixed position bitfields, much like we already have for deposit.

Backports commit 7ec8bab3deae643b1ce579c2d65a244f30708330 from qemu
This commit is contained in:
Richard Henderson 2018-03-01 13:13:49 -05:00 committed by Lioncash
parent 29932d0719
commit 8e0585dcb1
No known key found for this signature in database
GPG key ID: 4E3C3CC1031BA9C7
27 changed files with 489 additions and 3 deletions
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4
qemu/aarch64.h
View file

@ -3032,6 +3032,8 @@
#define tcg_gen_ext_i32_i64 tcg_gen_ext_i32_i64_aarch64
#define tcg_gen_extr32_i64 tcg_gen_extr32_i64_aarch64
#define tcg_gen_extr_i64_i32 tcg_gen_extr_i64_i32_aarch64
#define tcg_gen_extract_i32 tcg_gen_extract_i32_aarch64
#define tcg_gen_extract_i64 tcg_gen_extract_i64_aarch64
#define tcg_gen_extrh_i64_i32 tcg_gen_extrh_i64_i32_aarch64
#define tcg_gen_extrl_i64_i32 tcg_gen_extrl_i64_i32_aarch64
#define tcg_gen_extu_i32_i64 tcg_gen_extu_i32_i64_aarch64
@ -3123,6 +3125,8 @@
#define tcg_gen_setcond_i64 tcg_gen_setcond_i64_aarch64
#define tcg_gen_setcondi_i32 tcg_gen_setcondi_i32_aarch64
#define tcg_gen_setcondi_i64 tcg_gen_setcondi_i64_aarch64
#define tcg_gen_sextract_i32 tcg_gen_sextract_i32_aarch64
#define tcg_gen_sextract_i64 tcg_gen_sextract_i64_aarch64
#define tcg_gen_shifti_i64 tcg_gen_shifti_i64_aarch64
#define tcg_gen_shl_i32 tcg_gen_shl_i32_aarch64
#define tcg_gen_shl_i64 tcg_gen_shl_i64_aarch64

4
qemu/aarch64eb.h
View file

@ -3032,6 +3032,8 @@
#define tcg_gen_ext_i32_i64 tcg_gen_ext_i32_i64_aarch64eb
#define tcg_gen_extr32_i64 tcg_gen_extr32_i64_aarch64eb
#define tcg_gen_extr_i64_i32 tcg_gen_extr_i64_i32_aarch64eb
#define tcg_gen_extract_i32 tcg_gen_extract_i32_aarch64eb
#define tcg_gen_extract_i64 tcg_gen_extract_i64_aarch64eb
#define tcg_gen_extrh_i64_i32 tcg_gen_extrh_i64_i32_aarch64eb
#define tcg_gen_extrl_i64_i32 tcg_gen_extrl_i64_i32_aarch64eb
#define tcg_gen_extu_i32_i64 tcg_gen_extu_i32_i64_aarch64eb
@ -3123,6 +3125,8 @@
#define tcg_gen_setcond_i64 tcg_gen_setcond_i64_aarch64eb
#define tcg_gen_setcondi_i32 tcg_gen_setcondi_i32_aarch64eb
#define tcg_gen_setcondi_i64 tcg_gen_setcondi_i64_aarch64eb
#define tcg_gen_sextract_i32 tcg_gen_sextract_i32_aarch64eb
#define tcg_gen_sextract_i64 tcg_gen_sextract_i64_aarch64eb
#define tcg_gen_shifti_i64 tcg_gen_shifti_i64_aarch64eb
#define tcg_gen_shl_i32 tcg_gen_shl_i32_aarch64eb
#define tcg_gen_shl_i64 tcg_gen_shl_i64_aarch64eb

4
qemu/arm.h
View file

@ -3032,6 +3032,8 @@
#define tcg_gen_ext_i32_i64 tcg_gen_ext_i32_i64_arm
#define tcg_gen_extr32_i64 tcg_gen_extr32_i64_arm
#define tcg_gen_extr_i64_i32 tcg_gen_extr_i64_i32_arm
#define tcg_gen_extract_i32 tcg_gen_extract_i32_arm
#define tcg_gen_extract_i64 tcg_gen_extract_i64_arm
#define tcg_gen_extrh_i64_i32 tcg_gen_extrh_i64_i32_arm
#define tcg_gen_extrl_i64_i32 tcg_gen_extrl_i64_i32_arm
#define tcg_gen_extu_i32_i64 tcg_gen_extu_i32_i64_arm
@ -3123,6 +3125,8 @@
#define tcg_gen_setcond_i64 tcg_gen_setcond_i64_arm
#define tcg_gen_setcondi_i32 tcg_gen_setcondi_i32_arm
#define tcg_gen_setcondi_i64 tcg_gen_setcondi_i64_arm
#define tcg_gen_sextract_i32 tcg_gen_sextract_i32_arm
#define tcg_gen_sextract_i64 tcg_gen_sextract_i64_arm
#define tcg_gen_shifti_i64 tcg_gen_shifti_i64_arm
#define tcg_gen_shl_i32 tcg_gen_shl_i32_arm
#define tcg_gen_shl_i64 tcg_gen_shl_i64_arm

4
qemu/armeb.h
View file

@ -3032,6 +3032,8 @@
#define tcg_gen_ext_i32_i64 tcg_gen_ext_i32_i64_armeb
#define tcg_gen_extr32_i64 tcg_gen_extr32_i64_armeb
#define tcg_gen_extr_i64_i32 tcg_gen_extr_i64_i32_armeb
#define tcg_gen_extract_i32 tcg_gen_extract_i32_armeb
#define tcg_gen_extract_i64 tcg_gen_extract_i64_armeb
#define tcg_gen_extrh_i64_i32 tcg_gen_extrh_i64_i32_armeb
#define tcg_gen_extrl_i64_i32 tcg_gen_extrl_i64_i32_armeb
#define tcg_gen_extu_i32_i64 tcg_gen_extu_i32_i64_armeb
@ -3123,6 +3125,8 @@
#define tcg_gen_setcond_i64 tcg_gen_setcond_i64_armeb
#define tcg_gen_setcondi_i32 tcg_gen_setcondi_i32_armeb
#define tcg_gen_setcondi_i64 tcg_gen_setcondi_i64_armeb
#define tcg_gen_sextract_i32 tcg_gen_sextract_i32_armeb
#define tcg_gen_sextract_i64 tcg_gen_sextract_i64_armeb
#define tcg_gen_shifti_i64 tcg_gen_shifti_i64_armeb
#define tcg_gen_shl_i32 tcg_gen_shl_i32_armeb
#define tcg_gen_shl_i64 tcg_gen_shl_i64_armeb

4
qemu/header_gen.py
View file

@ -3038,6 +3038,8 @@ symbols = (
'tcg_gen_ext_i32_i64',
'tcg_gen_extr32_i64',
'tcg_gen_extr_i64_i32',
'tcg_gen_extract_i32',
'tcg_gen_extract_i64',
'tcg_gen_extrh_i64_i32',
'tcg_gen_extrl_i64_i32',
'tcg_gen_extu_i32_i64',
@ -3129,6 +3131,8 @@ symbols = (
'tcg_gen_setcond_i64',
'tcg_gen_setcondi_i32',
'tcg_gen_setcondi_i64',
'tcg_gen_sextract_i32',
'tcg_gen_sextract_i64',
'tcg_gen_shifti_i64',
'tcg_gen_shl_i32',
'tcg_gen_shl_i64',

4
qemu/m68k.h
View file

@ -3032,6 +3032,8 @@
#define tcg_gen_ext_i32_i64 tcg_gen_ext_i32_i64_m68k
#define tcg_gen_extr32_i64 tcg_gen_extr32_i64_m68k
#define tcg_gen_extr_i64_i32 tcg_gen_extr_i64_i32_m68k
#define tcg_gen_extract_i32 tcg_gen_extract_i32_m68k
#define tcg_gen_extract_i64 tcg_gen_extract_i64_m68k
#define tcg_gen_extrh_i64_i32 tcg_gen_extrh_i64_i32_m68k
#define tcg_gen_extrl_i64_i32 tcg_gen_extrl_i64_i32_m68k
#define tcg_gen_extu_i32_i64 tcg_gen_extu_i32_i64_m68k
@ -3123,6 +3125,8 @@
#define tcg_gen_setcond_i64 tcg_gen_setcond_i64_m68k
#define tcg_gen_setcondi_i32 tcg_gen_setcondi_i32_m68k
#define tcg_gen_setcondi_i64 tcg_gen_setcondi_i64_m68k
#define tcg_gen_sextract_i32 tcg_gen_sextract_i32_m68k
#define tcg_gen_sextract_i64 tcg_gen_sextract_i64_m68k
#define tcg_gen_shifti_i64 tcg_gen_shifti_i64_m68k
#define tcg_gen_shl_i32 tcg_gen_shl_i32_m68k
#define tcg_gen_shl_i64 tcg_gen_shl_i64_m68k

4
qemu/mips.h
View file

@ -3032,6 +3032,8 @@
#define tcg_gen_ext_i32_i64 tcg_gen_ext_i32_i64_mips
#define tcg_gen_extr32_i64 tcg_gen_extr32_i64_mips
#define tcg_gen_extr_i64_i32 tcg_gen_extr_i64_i32_mips
#define tcg_gen_extract_i32 tcg_gen_extract_i32_mips
#define tcg_gen_extract_i64 tcg_gen_extract_i64_mips
#define tcg_gen_extrh_i64_i32 tcg_gen_extrh_i64_i32_mips
#define tcg_gen_extrl_i64_i32 tcg_gen_extrl_i64_i32_mips
#define tcg_gen_extu_i32_i64 tcg_gen_extu_i32_i64_mips
@ -3123,6 +3125,8 @@
#define tcg_gen_setcond_i64 tcg_gen_setcond_i64_mips
#define tcg_gen_setcondi_i32 tcg_gen_setcondi_i32_mips
#define tcg_gen_setcondi_i64 tcg_gen_setcondi_i64_mips
#define tcg_gen_sextract_i32 tcg_gen_sextract_i32_mips
#define tcg_gen_sextract_i64 tcg_gen_sextract_i64_mips
#define tcg_gen_shifti_i64 tcg_gen_shifti_i64_mips
#define tcg_gen_shl_i32 tcg_gen_shl_i32_mips
#define tcg_gen_shl_i64 tcg_gen_shl_i64_mips

4
qemu/mips64.h
View file

@ -3032,6 +3032,8 @@
#define tcg_gen_ext_i32_i64 tcg_gen_ext_i32_i64_mips64
#define tcg_gen_extr32_i64 tcg_gen_extr32_i64_mips64
#define tcg_gen_extr_i64_i32 tcg_gen_extr_i64_i32_mips64
#define tcg_gen_extract_i32 tcg_gen_extract_i32_mips64
#define tcg_gen_extract_i64 tcg_gen_extract_i64_mips64
#define tcg_gen_extrh_i64_i32 tcg_gen_extrh_i64_i32_mips64
#define tcg_gen_extrl_i64_i32 tcg_gen_extrl_i64_i32_mips64
#define tcg_gen_extu_i32_i64 tcg_gen_extu_i32_i64_mips64
@ -3123,6 +3125,8 @@
#define tcg_gen_setcond_i64 tcg_gen_setcond_i64_mips64
#define tcg_gen_setcondi_i32 tcg_gen_setcondi_i32_mips64
#define tcg_gen_setcondi_i64 tcg_gen_setcondi_i64_mips64
#define tcg_gen_sextract_i32 tcg_gen_sextract_i32_mips64
#define tcg_gen_sextract_i64 tcg_gen_sextract_i64_mips64
#define tcg_gen_shifti_i64 tcg_gen_shifti_i64_mips64
#define tcg_gen_shl_i32 tcg_gen_shl_i32_mips64
#define tcg_gen_shl_i64 tcg_gen_shl_i64_mips64

4
qemu/mips64el.h
View file

@ -3032,6 +3032,8 @@
#define tcg_gen_ext_i32_i64 tcg_gen_ext_i32_i64_mips64el
#define tcg_gen_extr32_i64 tcg_gen_extr32_i64_mips64el
#define tcg_gen_extr_i64_i32 tcg_gen_extr_i64_i32_mips64el
#define tcg_gen_extract_i32 tcg_gen_extract_i32_mips64el
#define tcg_gen_extract_i64 tcg_gen_extract_i64_mips64el
#define tcg_gen_extrh_i64_i32 tcg_gen_extrh_i64_i32_mips64el
#define tcg_gen_extrl_i64_i32 tcg_gen_extrl_i64_i32_mips64el
#define tcg_gen_extu_i32_i64 tcg_gen_extu_i32_i64_mips64el
@ -3123,6 +3125,8 @@
#define tcg_gen_setcond_i64 tcg_gen_setcond_i64_mips64el
#define tcg_gen_setcondi_i32 tcg_gen_setcondi_i32_mips64el
#define tcg_gen_setcondi_i64 tcg_gen_setcondi_i64_mips64el
#define tcg_gen_sextract_i32 tcg_gen_sextract_i32_mips64el
#define tcg_gen_sextract_i64 tcg_gen_sextract_i64_mips64el
#define tcg_gen_shifti_i64 tcg_gen_shifti_i64_mips64el
#define tcg_gen_shl_i32 tcg_gen_shl_i32_mips64el
#define tcg_gen_shl_i64 tcg_gen_shl_i64_mips64el

4
qemu/mipsel.h
View file

@ -3032,6 +3032,8 @@
#define tcg_gen_ext_i32_i64 tcg_gen_ext_i32_i64_mipsel
#define tcg_gen_extr32_i64 tcg_gen_extr32_i64_mipsel
#define tcg_gen_extr_i64_i32 tcg_gen_extr_i64_i32_mipsel
#define tcg_gen_extract_i32 tcg_gen_extract_i32_mipsel
#define tcg_gen_extract_i64 tcg_gen_extract_i64_mipsel
#define tcg_gen_extrh_i64_i32 tcg_gen_extrh_i64_i32_mipsel
#define tcg_gen_extrl_i64_i32 tcg_gen_extrl_i64_i32_mipsel
#define tcg_gen_extu_i32_i64 tcg_gen_extu_i32_i64_mipsel
@ -3123,6 +3125,8 @@
#define tcg_gen_setcond_i64 tcg_gen_setcond_i64_mipsel
#define tcg_gen_setcondi_i32 tcg_gen_setcondi_i32_mipsel
#define tcg_gen_setcondi_i64 tcg_gen_setcondi_i64_mipsel
#define tcg_gen_sextract_i32 tcg_gen_sextract_i32_mipsel
#define tcg_gen_sextract_i64 tcg_gen_sextract_i64_mipsel
#define tcg_gen_shifti_i64 tcg_gen_shifti_i64_mipsel
#define tcg_gen_shl_i32 tcg_gen_shl_i32_mipsel
#define tcg_gen_shl_i64 tcg_gen_shl_i64_mipsel

4
qemu/powerpc.h
View file

@ -3032,6 +3032,8 @@
#define tcg_gen_ext_i32_i64 tcg_gen_ext_i32_i64_powerpc
#define tcg_gen_extr32_i64 tcg_gen_extr32_i64_powerpc
#define tcg_gen_extr_i64_i32 tcg_gen_extr_i64_i32_powerpc
#define tcg_gen_extract_i32 tcg_gen_extract_i32_powerpc
#define tcg_gen_extract_i64 tcg_gen_extract_i64_powerpc
#define tcg_gen_extrh_i64_i32 tcg_gen_extrh_i64_i32_powerpc
#define tcg_gen_extrl_i64_i32 tcg_gen_extrl_i64_i32_powerpc
#define tcg_gen_extu_i32_i64 tcg_gen_extu_i32_i64_powerpc
@ -3123,6 +3125,8 @@
#define tcg_gen_setcond_i64 tcg_gen_setcond_i64_powerpc
#define tcg_gen_setcondi_i32 tcg_gen_setcondi_i32_powerpc
#define tcg_gen_setcondi_i64 tcg_gen_setcondi_i64_powerpc
#define tcg_gen_sextract_i32 tcg_gen_sextract_i32_powerpc
#define tcg_gen_sextract_i64 tcg_gen_sextract_i64_powerpc
#define tcg_gen_shifti_i64 tcg_gen_shifti_i64_powerpc
#define tcg_gen_shl_i32 tcg_gen_shl_i32_powerpc
#define tcg_gen_shl_i64 tcg_gen_shl_i64_powerpc

4
qemu/sparc.h
View file

@ -3032,6 +3032,8 @@
#define tcg_gen_ext_i32_i64 tcg_gen_ext_i32_i64_sparc
#define tcg_gen_extr32_i64 tcg_gen_extr32_i64_sparc
#define tcg_gen_extr_i64_i32 tcg_gen_extr_i64_i32_sparc
#define tcg_gen_extract_i32 tcg_gen_extract_i32_sparc
#define tcg_gen_extract_i64 tcg_gen_extract_i64_sparc
#define tcg_gen_extrh_i64_i32 tcg_gen_extrh_i64_i32_sparc
#define tcg_gen_extrl_i64_i32 tcg_gen_extrl_i64_i32_sparc
#define tcg_gen_extu_i32_i64 tcg_gen_extu_i32_i64_sparc
@ -3123,6 +3125,8 @@
#define tcg_gen_setcond_i64 tcg_gen_setcond_i64_sparc
#define tcg_gen_setcondi_i32 tcg_gen_setcondi_i32_sparc
#define tcg_gen_setcondi_i64 tcg_gen_setcondi_i64_sparc
#define tcg_gen_sextract_i32 tcg_gen_sextract_i32_sparc
#define tcg_gen_sextract_i64 tcg_gen_sextract_i64_sparc
#define tcg_gen_shifti_i64 tcg_gen_shifti_i64_sparc
#define tcg_gen_shl_i32 tcg_gen_shl_i32_sparc
#define tcg_gen_shl_i64 tcg_gen_shl_i64_sparc

4
qemu/sparc64.h
View file

@ -3032,6 +3032,8 @@
#define tcg_gen_ext_i32_i64 tcg_gen_ext_i32_i64_sparc64
#define tcg_gen_extr32_i64 tcg_gen_extr32_i64_sparc64
#define tcg_gen_extr_i64_i32 tcg_gen_extr_i64_i32_sparc64
#define tcg_gen_extract_i32 tcg_gen_extract_i32_sparc64
#define tcg_gen_extract_i64 tcg_gen_extract_i64_sparc64
#define tcg_gen_extrh_i64_i32 tcg_gen_extrh_i64_i32_sparc64
#define tcg_gen_extrl_i64_i32 tcg_gen_extrl_i64_i32_sparc64
#define tcg_gen_extu_i32_i64 tcg_gen_extu_i32_i64_sparc64
@ -3123,6 +3125,8 @@
#define tcg_gen_setcond_i64 tcg_gen_setcond_i64_sparc64
#define tcg_gen_setcondi_i32 tcg_gen_setcondi_i32_sparc64
#define tcg_gen_setcondi_i64 tcg_gen_setcondi_i64_sparc64
#define tcg_gen_sextract_i32 tcg_gen_sextract_i32_sparc64
#define tcg_gen_sextract_i64 tcg_gen_sextract_i64_sparc64
#define tcg_gen_shifti_i64 tcg_gen_shifti_i64_sparc64
#define tcg_gen_shl_i32 tcg_gen_shl_i32_sparc64
#define tcg_gen_shl_i64 tcg_gen_shl_i64_sparc64

20
qemu/tcg/README
View file

@ -309,11 +309,27 @@ The bitfield is described by POS/LEN, which are immediate values:
LEN - the length of the bitfield
POS - the position of the first bit, counting from the LSB
For example, pos=8, len=4 indicates a 4-bit field at bit 8.
This operation would be equivalent to
For example, "deposit_i32 dest, t1, t2, 8, 4" indicates a 4-bit field
at bit 8. This operation would be equivalent to
dest = (t1 & ~0x0f00) | ((t2 << 8) & 0x0f00)
* extract_i32/i64 dest, t1, pos, len
* sextract_i32/i64 dest, t1, pos, len
Extract a bitfield from T1, placing the result in DEST.
The bitfield is described by POS/LEN, which are immediate values,
as above for deposit. For extract_*, the result will be extended
to the left with zeros; for sextract_*, the result will be extended
to the left with copies of the bitfield sign bit at pos + len - 1.
For example, "sextract_i32 dest, t1, 8, 4" indicates a 4-bit field
at bit 8. This operation would be equivalent to
dest = (t1 << 20) >> 28
(using an arithmetic right shift).
* extrl_i64_i32 t0, t1
For 64-bit hosts only, extract the low 32-bits of input T1 and place it

4
qemu/tcg/aarch64/tcg-target.h
View file

@ -63,6 +63,8 @@ typedef enum {
#define TCG_TARGET_HAS_nand_i32 0
#define TCG_TARGET_HAS_nor_i32 0
#define TCG_TARGET_HAS_deposit_i32 1
#define TCG_TARGET_HAS_extract_i32 0
#define TCG_TARGET_HAS_sextract_i32 0
#define TCG_TARGET_HAS_movcond_i32 1
#define TCG_TARGET_HAS_add2_i32 1
#define TCG_TARGET_HAS_sub2_i32 1
@ -93,6 +95,8 @@ typedef enum {
#define TCG_TARGET_HAS_nand_i64 0
#define TCG_TARGET_HAS_nor_i64 0
#define TCG_TARGET_HAS_deposit_i64 1
#define TCG_TARGET_HAS_extract_i64 0
#define TCG_TARGET_HAS_sextract_i64 0
#define TCG_TARGET_HAS_movcond_i64 1
#define TCG_TARGET_HAS_add2_i64 1
#define TCG_TARGET_HAS_sub2_i64 1

2
qemu/tcg/arm/tcg-target.h
View file

@ -81,6 +81,8 @@ extern bool use_idiv_instructions_rt;
#define TCG_TARGET_HAS_nand_i32 0
#define TCG_TARGET_HAS_nor_i32 0
#define TCG_TARGET_HAS_deposit_i32 1
#define TCG_TARGET_HAS_extract_i32 0
#define TCG_TARGET_HAS_sextract_i32 0
#define TCG_TARGET_HAS_movcond_i32 1
#define TCG_TARGET_HAS_mulu2_i32 1
#define TCG_TARGET_HAS_muls2_i32 1

4
qemu/tcg/i386/tcg-target.h
View file

@ -94,6 +94,8 @@ extern bool have_bmi1;
#define TCG_TARGET_HAS_nand_i32 0
#define TCG_TARGET_HAS_nor_i32 0
#define TCG_TARGET_HAS_deposit_i32 1
#define TCG_TARGET_HAS_extract_i32 0
#define TCG_TARGET_HAS_sextract_i32 0
#define TCG_TARGET_HAS_movcond_i32 1
#define TCG_TARGET_HAS_add2_i32 1
#define TCG_TARGET_HAS_sub2_i32 1
@ -124,6 +126,8 @@ extern bool have_bmi1;
#define TCG_TARGET_HAS_nand_i64 0
#define TCG_TARGET_HAS_nor_i64 0
#define TCG_TARGET_HAS_deposit_i64 1
#define TCG_TARGET_HAS_extract_i64 0
#define TCG_TARGET_HAS_sextract_i64 0
#define TCG_TARGET_HAS_movcond_i64 1
#define TCG_TARGET_HAS_add2_i64 1
#define TCG_TARGET_HAS_sub2_i64 1

2
qemu/tcg/mips/tcg-target.h
View file

@ -158,6 +158,8 @@ extern bool use_mips32r2_instructions;
#define TCG_TARGET_HAS_movcond_i32 use_movnz_instructions
#define TCG_TARGET_HAS_bswap16_i32 use_mips32r2_instructions
#define TCG_TARGET_HAS_deposit_i32 use_mips32r2_instructions
#define TCG_TARGET_HAS_extract_i32 0
#define TCG_TARGET_HAS_sextract_i32 0
#define TCG_TARGET_HAS_ext8s_i32 use_mips32r2_instructions
#define TCG_TARGET_HAS_ext16s_i32 use_mips32r2_instructions
#define TCG_TARGET_HAS_rot_i32 use_mips32r2_instructions

29
qemu/tcg/optimize.c
View file

@ -889,6 +889,19 @@ void tcg_optimize(TCGContext *s)
temps[args[2]].mask);
break;
CASE_OP_32_64(extract):
mask = extract64(temps[args[1]].mask, args[2], args[3]);
if (args[2] == 0) {
affected = temps[args[1]].mask & ~mask;
}
break;
CASE_OP_32_64(sextract):
mask = sextract64(temps[args[1]].mask, args[2], args[3]);
if (args[2] == 0 && (tcg_target_long)mask >= 0) {
affected = temps[args[1]].mask & ~mask;
}
break;
CASE_OP_32_64(or):
CASE_OP_32_64(xor):
mask = temps[args[1]].mask | temps[args[2]].mask;
@ -1059,6 +1072,22 @@ void tcg_optimize(TCGContext *s)
}
goto do_default;
CASE_OP_32_64(extract):
if (temp_is_const(s, args[1])) {
tmp = extract64(temps[args[1]].val, args[2], args[3]);
tcg_opt_gen_movi(s, op, args, args[0], tmp);
break;
}
goto do_default;
CASE_OP_32_64(sextract):
if (temp_is_const(s, args[1])) {
tmp = sextract64(temps[args[1]].val, args[2], args[3]);
tcg_opt_gen_movi(s, op, args, args[0], tmp);
break;
}
goto do_default;
CASE_OP_32_64(setcond):
tmp = do_constant_folding_cond(s, opc, args[1], args[2], args[3]);
if (tmp != 2) {

4
qemu/tcg/ppc/tcg-target.h
View file

@ -69,6 +69,8 @@ typedef enum {
#define TCG_TARGET_HAS_nand_i32 1
#define TCG_TARGET_HAS_nor_i32 1
#define TCG_TARGET_HAS_deposit_i32 1
#define TCG_TARGET_HAS_extract_i32 0
#define TCG_TARGET_HAS_sextract_i32 0
#define TCG_TARGET_HAS_movcond_i32 1
#define TCG_TARGET_HAS_mulu2_i32 0
#define TCG_TARGET_HAS_muls2_i32 0
@ -100,6 +102,8 @@ typedef enum {
#define TCG_TARGET_HAS_nand_i64 1
#define TCG_TARGET_HAS_nor_i64 1
#define TCG_TARGET_HAS_deposit_i64 1
#define TCG_TARGET_HAS_extract_i64 0
#define TCG_TARGET_HAS_sextract_i64 0
#define TCG_TARGET_HAS_movcond_i64 1
#define TCG_TARGET_HAS_add2_i64 1
#define TCG_TARGET_HAS_sub2_i64 1

4
qemu/tcg/s390/tcg-target.h
View file

@ -66,6 +66,8 @@ typedef enum TCGReg {
#define TCG_TARGET_HAS_nand_i32 0
#define TCG_TARGET_HAS_nor_i32 0
#define TCG_TARGET_HAS_deposit_i32 1
#define TCG_TARGET_HAS_extract_i32 0
#define TCG_TARGET_HAS_sextract_i32 0
#define TCG_TARGET_HAS_movcond_i32 1
#define TCG_TARGET_HAS_add2_i32 1
#define TCG_TARGET_HAS_sub2_i32 1
@ -95,6 +97,8 @@ typedef enum TCGReg {
#define TCG_TARGET_HAS_nand_i64 0
#define TCG_TARGET_HAS_nor_i64 0
#define TCG_TARGET_HAS_deposit_i64 1
#define TCG_TARGET_HAS_extract_i64 0
#define TCG_TARGET_HAS_sextract_i64 0
#define TCG_TARGET_HAS_movcond_i64 1
#define TCG_TARGET_HAS_add2_i64 1
#define TCG_TARGET_HAS_sub2_i64 1

4
qemu/tcg/sparc/tcg-target.h
View file

@ -111,6 +111,8 @@ extern bool use_vis3_instructions;
#define TCG_TARGET_HAS_nand_i32 0
#define TCG_TARGET_HAS_nor_i32 0
#define TCG_TARGET_HAS_deposit_i32 0
#define TCG_TARGET_HAS_extract_i32 0
#define TCG_TARGET_HAS_sextract_i32 0
#define TCG_TARGET_HAS_movcond_i32 1
#define TCG_TARGET_HAS_add2_i32 1
#define TCG_TARGET_HAS_sub2_i32 1
@ -141,6 +143,8 @@ extern bool use_vis3_instructions;
#define TCG_TARGET_HAS_nand_i64 0
#define TCG_TARGET_HAS_nor_i64 0
#define TCG_TARGET_HAS_deposit_i64 0
#define TCG_TARGET_HAS_extract_i64 0
#define TCG_TARGET_HAS_sextract_i64 0
#define TCG_TARGET_HAS_movcond_i64 1
#define TCG_TARGET_HAS_add2_i64 1
#define TCG_TARGET_HAS_sub2_i64 1

337
qemu/tcg/tcg-op.c
View file

@ -559,6 +559,138 @@ void tcg_gen_deposit_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 ar
tcg_temp_free_i32(s, t1);
}
void tcg_gen_extract_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg,
unsigned int ofs, unsigned int len)
{
tcg_debug_assert(ofs < 32);
tcg_debug_assert(len > 0);
tcg_debug_assert(len <= 32);
tcg_debug_assert(ofs + len <= 32);
/* Canonicalize certain special cases, even if extract is supported. */
if (ofs + len == 32) {
tcg_gen_shri_i32(s, ret, arg, 32 - len);
return;
}
if (ofs == 0) {
tcg_gen_andi_i32(s, ret, arg, (1u << len) - 1);
return;
}
if (TCG_TARGET_HAS_extract_i32
&& TCG_TARGET_extract_i32_valid(ofs, len)) {
tcg_gen_op4ii_i32(s, INDEX_op_extract_i32, ret, arg, ofs, len);
return;
}
/* Assume that zero-extension, if available, is cheaper than a shift. */
switch (ofs + len) {
case 16:
if (TCG_TARGET_HAS_ext16u_i32) {
tcg_gen_ext16u_i32(s, ret, arg);
tcg_gen_shri_i32(s, ret, ret, ofs);
return;
}
break;
case 8:
if (TCG_TARGET_HAS_ext8u_i32) {
tcg_gen_ext8u_i32(s, ret, arg);
tcg_gen_shri_i32(s, ret, ret, ofs);
return;
}
break;
}
/* ??? Ideally we'd know what values are available for immediate AND.
Assume that 8 bits are available, plus the special case of 16,
so that we get ext8u, ext16u. */
switch (len) {
case 1:
case 2:
case 3:
case 4:
case 5:
case 6:
case 7:
case 8: case 16:
tcg_gen_shri_i32(s, ret, arg, ofs);
tcg_gen_andi_i32(s, ret, ret, (1u << len) - 1);
break;
default:
tcg_gen_shli_i32(s, ret, arg, 32 - len - ofs);
tcg_gen_shri_i32(s, ret, ret, 32 - len);
break;
}
}
void tcg_gen_sextract_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg,
unsigned int ofs, unsigned int len)
{
tcg_debug_assert(ofs < 32);
tcg_debug_assert(len > 0);
tcg_debug_assert(len <= 32);
tcg_debug_assert(ofs + len <= 32);
/* Canonicalize certain special cases, even if extract is supported. */
if (ofs + len == 32) {
tcg_gen_sari_i32(s, ret, arg, 32 - len);
return;
}
if (ofs == 0) {
switch (len) {
case 16:
tcg_gen_ext16s_i32(s, ret, arg);
return;
case 8:
tcg_gen_ext8s_i32(s, ret, arg);
return;
}
}
if (TCG_TARGET_HAS_sextract_i32
&& TCG_TARGET_extract_i32_valid(ofs, len)) {
tcg_gen_op4ii_i32(s, INDEX_op_sextract_i32, ret, arg, ofs, len);
return;
}
/* Assume that sign-extension, if available, is cheaper than a shift. */
switch (ofs + len) {
case 16:
if (TCG_TARGET_HAS_ext16s_i32) {
tcg_gen_ext16s_i32(s, ret, arg);
tcg_gen_sari_i32(s, ret, ret, ofs);
return;
}
break;
case 8:
if (TCG_TARGET_HAS_ext8s_i32) {
tcg_gen_ext8s_i32(s, ret, arg);
tcg_gen_sari_i32(s, ret, ret, ofs);
return;
}
break;
}
switch (len) {
case 16:
if (TCG_TARGET_HAS_ext16s_i32) {
tcg_gen_shri_i32(s, ret, arg, ofs);
tcg_gen_ext16s_i32(s, ret, ret);
return;
}
break;
case 8:
if (TCG_TARGET_HAS_ext8s_i32) {
tcg_gen_shri_i32(s, ret, arg, ofs);
tcg_gen_ext8s_i32(s, ret, ret);
return;
}
break;
}
tcg_gen_shli_i32(s, ret, arg, 32 - len - ofs);
tcg_gen_sari_i32(s, ret, ret, 32 - len);
}
void tcg_gen_movcond_i32(TCGContext *s, TCGCond cond, TCGv_i32 ret, TCGv_i32 c1,
TCGv_i32 c2, TCGv_i32 v1, TCGv_i32 v2)
{
@ -1634,6 +1766,211 @@ void tcg_gen_deposit_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 ar
tcg_temp_free_i64(s, t1);
}
void tcg_gen_extract_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg,
unsigned int ofs, unsigned int len)
{
tcg_debug_assert(ofs < 64);
tcg_debug_assert(len > 0);
tcg_debug_assert(len <= 64);
tcg_debug_assert(ofs + len <= 64);
/* Canonicalize certain special cases, even if extract is supported. */
if (ofs + len == 64) {
tcg_gen_shri_i64(s, ret, arg, 64 - len);
return;
}
if (ofs == 0) {
tcg_gen_andi_i64(s, ret, arg, (1ull << len) - 1);
return;
}
if (TCG_TARGET_REG_BITS == 32) {
/* Look for a 32-bit extract within one of the two words. */
if (ofs >= 32) {
tcg_gen_extract_i32(s, TCGV_LOW(ret), TCGV_HIGH(arg), ofs - 32, len);
tcg_gen_movi_i32(s, TCGV_HIGH(ret), 0);
return;
}
if (ofs + len <= 32) {
tcg_gen_extract_i32(s, TCGV_LOW(ret), TCGV_LOW(arg), ofs, len);
tcg_gen_movi_i32(s, TCGV_HIGH(ret), 0);
return;
}
/* The field is split across two words. One double-word
shift is better than two double-word shifts. */
goto do_shift_and;
}
if (TCG_TARGET_HAS_extract_i64
&& TCG_TARGET_extract_i64_valid(ofs, len)) {
tcg_gen_op4ii_i64(s, INDEX_op_extract_i64, ret, arg, ofs, len);
return;
}
/* Assume that zero-extension, if available, is cheaper than a shift. */
switch (ofs + len) {
case 32:
if (TCG_TARGET_HAS_ext32u_i64) {
tcg_gen_ext32u_i64(s, ret, arg);
tcg_gen_shri_i64(s, ret, ret, ofs);
return;
}
break;
case 16:
if (TCG_TARGET_HAS_ext16u_i64) {
tcg_gen_ext16u_i64(s, ret, arg);
tcg_gen_shri_i64(s, ret, ret, ofs);
return;
}
break;
case 8:
if (TCG_TARGET_HAS_ext8u_i64) {
tcg_gen_ext8u_i64(s, ret, arg);
tcg_gen_shri_i64(s, ret, ret, ofs);
return;
}
break;
}
/* ??? Ideally we'd know what values are available for immediate AND.
Assume that 8 bits are available, plus the special cases of 16 and 32,
so that we get ext8u, ext16u, and ext32u. */
switch (len) {
case 1:
case 2:
case 3:
case 4:
case 5:
case 6:
case 7:
case 8: case 16: case 32:
do_shift_and:
tcg_gen_shri_i64(s, ret, arg, ofs);
tcg_gen_andi_i64(s, ret, ret, (1ull << len) - 1);
break;
default:
tcg_gen_shli_i64(s, ret, arg, 64 - len - ofs);
tcg_gen_shri_i64(s, ret, ret, 64 - len);
break;
}
}
void tcg_gen_sextract_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg,
unsigned int ofs, unsigned int len)
{
tcg_debug_assert(ofs < 64);
tcg_debug_assert(len > 0);
tcg_debug_assert(len <= 64);
tcg_debug_assert(ofs + len <= 64);
/* Canonicalize certain special cases, even if sextract is supported. */
if (ofs + len == 64) {
tcg_gen_sari_i64(s, ret, arg, 64 - len);
return;
}
if (ofs == 0) {
switch (len) {
case 32:
tcg_gen_ext32s_i64(s, ret, arg);
return;
case 16:
tcg_gen_ext16s_i64(s, ret, arg);
return;
case 8:
tcg_gen_ext8s_i64(s, ret, arg);
return;
}
}
if (TCG_TARGET_REG_BITS == 32) {
/* Look for a 32-bit extract within one of the two words. */
if (ofs >= 32) {
tcg_gen_sextract_i32(s, TCGV_LOW(ret), TCGV_HIGH(arg), ofs - 32, len);
} else if (ofs + len <= 32) {
tcg_gen_sextract_i32(s, TCGV_LOW(ret), TCGV_LOW(arg), ofs, len);
} else if (ofs == 0) {
tcg_gen_mov_i32(s, TCGV_LOW(ret), TCGV_LOW(arg));
tcg_gen_sextract_i32(s, TCGV_HIGH(ret), TCGV_HIGH(arg), 0, len - 32);
return;
} else if (len > 32) {
TCGv_i32 t = tcg_temp_new_i32(s);
/* Extract the bits for the high word normally. */
tcg_gen_sextract_i32(s, t, TCGV_HIGH(arg), ofs + 32, len - 32);
/* Shift the field down for the low part. */
tcg_gen_shri_i64(s, ret, arg, ofs);
/* Overwrite the shift into the high part. */
tcg_gen_mov_i32(s, TCGV_HIGH(ret), t);
tcg_temp_free_i32(s, t);
return;
} else {
/* Shift the field down for the low part, such that the
field sits at the MSB. */
tcg_gen_shri_i64(s, ret, arg, ofs + len - 32);
/* Shift the field down from the MSB, sign extending. */
tcg_gen_sari_i32(s, TCGV_LOW(ret), TCGV_LOW(ret), 32 - len);
}
/* Sign-extend the field from 32 bits. */
tcg_gen_sari_i32(s, TCGV_HIGH(ret), TCGV_LOW(ret), 31);
return;
}
if (TCG_TARGET_HAS_sextract_i64
&& TCG_TARGET_extract_i64_valid(ofs, len)) {
tcg_gen_op4ii_i64(s, INDEX_op_sextract_i64, ret, arg, ofs, len);
return;
}
/* Assume that sign-extension, if available, is cheaper than a shift. */
switch (ofs + len) {
case 32:
if (TCG_TARGET_HAS_ext32s_i64) {
tcg_gen_ext32s_i64(s, ret, arg);
tcg_gen_sari_i64(s, ret, ret, ofs);
return;
}
break;
case 16:
if (TCG_TARGET_HAS_ext16s_i64) {
tcg_gen_ext16s_i64(s, ret, arg);
tcg_gen_sari_i64(s, ret, ret, ofs);
return;
}
break;
case 8:
if (TCG_TARGET_HAS_ext8s_i64) {
tcg_gen_ext8s_i64(s, ret, arg);
tcg_gen_sari_i64(s, ret, ret, ofs);
return;
}
break;
}
switch (len) {
case 32:
if (TCG_TARGET_HAS_ext32s_i64) {
tcg_gen_shri_i64(s, ret, arg, ofs);
tcg_gen_ext32s_i64(s, ret, ret);
return;
}
break;
case 16:
if (TCG_TARGET_HAS_ext16s_i64) {
tcg_gen_shri_i64(s, ret, arg, ofs);
tcg_gen_ext16s_i64(s, ret, ret);
return;
}
break;
case 8:
if (TCG_TARGET_HAS_ext8s_i64) {
tcg_gen_shri_i64(s, ret, arg, ofs);
tcg_gen_ext8s_i64(s, ret, ret);
return;
}
break;
}
tcg_gen_shli_i64(s, ret, arg, 64 - len - ofs);
tcg_gen_sari_i64(s, ret, ret, 64 - len);
}
void tcg_gen_movcond_i64(TCGContext *s, TCGCond cond, TCGv_i64 ret, TCGv_i64 c1,
TCGv_i64 c2, TCGv_i64 v1, TCGv_i64 v2)
{

12
qemu/tcg/tcg-op.h
View file

@ -300,6 +300,10 @@ void tcg_gen_rotr_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
void tcg_gen_rotri_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg1, unsigned arg2);
void tcg_gen_deposit_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2,
unsigned int ofs, unsigned int len);
void tcg_gen_extract_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg,
unsigned int ofs, unsigned int len);
void tcg_gen_sextract_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg,
unsigned int ofs, unsigned int len);
void tcg_gen_brcond_i32(TCGContext *s, TCGCond cond, TCGv_i32 arg1, TCGv_i32 arg2, TCGLabel *l);
void tcg_gen_brcondi_i32(TCGContext *s, TCGCond cond, TCGv_i32 arg1, int32_t arg2, TCGLabel *l);
void tcg_gen_setcond_i32(TCGContext *s, TCGCond cond, TCGv_i32 ret,
@ -469,6 +473,10 @@ void tcg_gen_rotr_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
void tcg_gen_rotri_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, unsigned arg2);
void tcg_gen_deposit_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2,
unsigned int ofs, unsigned int len);
void tcg_gen_extract_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg,
unsigned int ofs, unsigned int len);
void tcg_gen_sextract_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg,
unsigned int ofs, unsigned int len);
void tcg_gen_brcond_i64(TCGContext *s, TCGCond cond, TCGv_i64 arg1, TCGv_i64 arg2, TCGLabel *l);
void tcg_gen_brcondi_i64(TCGContext *s, TCGCond cond, TCGv_i64 arg1, int64_t arg2, TCGLabel *l);
void tcg_gen_setcond_i64(TCGContext *s, TCGCond cond, TCGv_i64 ret,
@ -953,6 +961,8 @@ void tcg_gen_atomic_xor_fetch_i64(TCGContext *, TCGv_i64, TCGv, TCGv_i64, TCGArg
#define tcg_gen_rotr_tl tcg_gen_rotr_i64
#define tcg_gen_rotri_tl tcg_gen_rotri_i64
#define tcg_gen_deposit_tl tcg_gen_deposit_i64
#define tcg_gen_extract_tl tcg_gen_extract_i64
#define tcg_gen_sextract_tl tcg_gen_sextract_i64
#define tcg_const_tl tcg_const_i64
#define tcg_const_local_tl tcg_const_local_i64
#define tcg_gen_movcond_tl tcg_gen_movcond_i64
@ -1041,6 +1051,8 @@ void tcg_gen_atomic_xor_fetch_i64(TCGContext *, TCGv_i64, TCGv, TCGv_i64, TCGArg
#define tcg_gen_rotr_tl tcg_gen_rotr_i32
#define tcg_gen_rotri_tl tcg_gen_rotri_i32
#define tcg_gen_deposit_tl tcg_gen_deposit_i32
#define tcg_gen_extract_tl tcg_gen_extract_i32
#define tcg_gen_sextract_tl tcg_gen_sextract_i32
#define tcg_const_tl tcg_const_i32
#define tcg_const_local_tl tcg_const_local_i32
#define tcg_gen_movcond_tl tcg_gen_movcond_i32

4
qemu/tcg/tcg-opc.h
View file

@ -82,6 +82,8 @@ DEF(sar_i32, 1, 2, 0, 0)
DEF(rotl_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rot_i32))
DEF(rotr_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rot_i32))
DEF(deposit_i32, 1, 2, 2, IMPL(TCG_TARGET_HAS_deposit_i32))
DEF(extract_i32, 1, 1, 2, IMPL(TCG_TARGET_HAS_extract_i32))
DEF(sextract_i32, 1, 1, 2, IMPL(TCG_TARGET_HAS_sextract_i32))
DEF(brcond_i32, 0, 2, 2, TCG_OPF_BB_END)
@ -144,6 +146,8 @@ DEF(sar_i64, 1, 2, 0, IMPL64)
DEF(rotl_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_rot_i64))
DEF(rotr_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_rot_i64))
DEF(deposit_i64, 1, 2, 2, IMPL64 | IMPL(TCG_TARGET_HAS_deposit_i64))
DEF(extract_i64, 1, 1, 2, IMPL64 | IMPL(TCG_TARGET_HAS_extract_i64))
DEF(sextract_i64, 1, 1, 2, IMPL64 | IMPL(TCG_TARGET_HAS_sextract_i64))
/* size changing ops */
DEF(ext_i32_i64, 1, 1, 0, IMPL64)

10
qemu/tcg/tcg.h
View file

@ -115,6 +115,8 @@ typedef uint64_t TCGRegSet;
#define TCG_TARGET_HAS_nand_i64 0
#define TCG_TARGET_HAS_nor_i64 0
#define TCG_TARGET_HAS_deposit_i64 0
#define TCG_TARGET_HAS_extract_i64 0
#define TCG_TARGET_HAS_sextract_i64 0
#define TCG_TARGET_HAS_movcond_i64 0
#define TCG_TARGET_HAS_add2_i64 0
#define TCG_TARGET_HAS_sub2_i64 0
@ -133,6 +135,12 @@ typedef uint64_t TCGRegSet;
#ifndef TCG_TARGET_deposit_i64_valid
#define TCG_TARGET_deposit_i64_valid(ofs, len) 1
#endif
#ifndef TCG_TARGET_extract_i32_valid
#define TCG_TARGET_extract_i32_valid(ofs, len) 1
#endif
#ifndef TCG_TARGET_extract_i64_valid
#define TCG_TARGET_extract_i64_valid(ofs, len) 1
#endif
/* Only one of DIV or DIV2 should be defined. */
#if defined(TCG_TARGET_HAS_div_i32)
@ -1003,7 +1011,7 @@ static inline bool tcg_op_buf_full(TCGContext *tcg_ctx)
}
// UNICORN: Added
#define TCG_OP_DEFS_TABLE_SIZE 125
#define TCG_OP_DEFS_TABLE_SIZE 129
extern const TCGOpDef tcg_op_defs_org[TCG_OP_DEFS_TABLE_SIZE];
typedef struct TCGTargetOpDef {

4
qemu/x86_64.h
View file

@ -3032,6 +3032,8 @@
#define tcg_gen_ext_i32_i64 tcg_gen_ext_i32_i64_x86_64
#define tcg_gen_extr32_i64 tcg_gen_extr32_i64_x86_64
#define tcg_gen_extr_i64_i32 tcg_gen_extr_i64_i32_x86_64
#define tcg_gen_extract_i32 tcg_gen_extract_i32_x86_64
#define tcg_gen_extract_i64 tcg_gen_extract_i64_x86_64
#define tcg_gen_extrh_i64_i32 tcg_gen_extrh_i64_i32_x86_64
#define tcg_gen_extrl_i64_i32 tcg_gen_extrl_i64_i32_x86_64
#define tcg_gen_extu_i32_i64 tcg_gen_extu_i32_i64_x86_64
@ -3123,6 +3125,8 @@
#define tcg_gen_setcond_i64 tcg_gen_setcond_i64_x86_64
#define tcg_gen_setcondi_i32 tcg_gen_setcondi_i32_x86_64
#define tcg_gen_setcondi_i64 tcg_gen_setcondi_i64_x86_64
#define tcg_gen_sextract_i32 tcg_gen_sextract_i32_x86_64
#define tcg_gen_sextract_i64 tcg_gen_sextract_i64_x86_64
#define tcg_gen_shifti_i64 tcg_gen_shifti_i64_x86_64
#define tcg_gen_shl_i32 tcg_gen_shl_i32_x86_64
#define tcg_gen_shl_i64 tcg_gen_shl_i64_x86_64