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https://github.com/yuzu-emu/unicorn.git
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target/arm: Use the any cpu model instead of cortex-a57
The Cortex-A57 doesn't allow use of v8.1+ architecture instructions
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parent
b90333a531
commit
8e161bb723
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@ -64,7 +64,9 @@ static int machvirt_init(struct uc_struct *uc, MachineState *machine)
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int n;
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int n;
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if (!cpu_model) {
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if (!cpu_model) {
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cpu_model = "cortex-a57"; // ARM64
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// Unicorn: "any" used instead to allow use of ARMv8.1+ instructions.
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//cpu_model = "cortex-a57"; // ARM64
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cpu_model = "any";
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}
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}
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for (n = 0; n < smp_cpus; n++) {
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for (n = 0; n < smp_cpus; n++) {
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@ -188,7 +188,7 @@ static void aarch64_a53_initfn(struct uc_struct *uc, Object *obj, void *opaque)
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define_arm_cp_regs(cpu, cortex_a57_a53_cp_reginfo);
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define_arm_cp_regs(cpu, cortex_a57_a53_cp_reginfo);
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}
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}
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#ifdef CONFIG_USER_ONLY
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// Unicorn: enabled for the general use-case as well.
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static void aarch64_any_initfn(struct uc_struct *uc, Object *obj, void *opaque)
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static void aarch64_any_initfn(struct uc_struct *uc, Object *obj, void *opaque)
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{
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{
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ARMCPU *cpu = ARM_CPU(uc, obj);
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ARMCPU *cpu = ARM_CPU(uc, obj);
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@ -212,7 +212,6 @@ static void aarch64_any_initfn(struct uc_struct *uc, Object *obj, void *opaque)
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cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */
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cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */
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cpu->dcz_blocksize = 7; /* 512 bytes */
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cpu->dcz_blocksize = 7; /* 512 bytes */
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}
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}
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#endif
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typedef struct ARMCPUInfo {
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typedef struct ARMCPUInfo {
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const char *name;
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const char *name;
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@ -223,9 +222,8 @@ typedef struct ARMCPUInfo {
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static const ARMCPUInfo aarch64_cpus[] = {
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static const ARMCPUInfo aarch64_cpus[] = {
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{ "cortex-a57", aarch64_a57_initfn },
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{ "cortex-a57", aarch64_a57_initfn },
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{ "cortex-a53", aarch64_a53_initfn },
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{ "cortex-a53", aarch64_a53_initfn },
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#ifdef CONFIG_USER_ONLY
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// Unicorn: enabled for the general use case as well
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{ "any", aarch64_any_initfn },
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{ "any", aarch64_any_initfn },
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#endif
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{ NULL }
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{ NULL }
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};
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};
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