Arm support ported. (#736)

* Fix for MIPS issue.

* Sparc support added.

* M68K support added.

* Arm support ported.

* Fix issue with VS2015 shlobj.h file

include/unicorn/platform.h

@@ -198,6 +198,12 @@ static void usleep(const int64_t &t)
 
 // misc support
 #if defined(_MSC_VER)
+#ifdef  _WIN64
+typedef signed __int64    ssize_t;
+#else
+typedef _W64 signed int   ssize_t;
+#endif
+
 #define va_copy(d,s) ((d) = (s))
 #define strcasecmp	_stricmp
 #if (_MSC_VER < MSC_VER_VS2015)

msvc/unicorn.sln

@@ -122,60 +122,93 @@ Global
 		{F8053D66-8267-433A-BF2C-E07E2298C338}.Release|x64.ActiveCfg = Release|x64
 		{F8053D66-8267-433A-BF2C-E07E2298C338}.Release|x64.Build.0 = Release|x64
 		{2A7F483F-CD19-4F84-BBDA-B6A1865E2773}.Debug|Win32.ActiveCfg = Debug|Win32
+		{2A7F483F-CD19-4F84-BBDA-B6A1865E2773}.Debug|Win32.Build.0 = Debug|Win32
 		{2A7F483F-CD19-4F84-BBDA-B6A1865E2773}.Debug|x64.ActiveCfg = Debug|x64
+		{2A7F483F-CD19-4F84-BBDA-B6A1865E2773}.Debug|x64.Build.0 = Debug|x64
 		{2A7F483F-CD19-4F84-BBDA-B6A1865E2773}.Release|Win32.ActiveCfg = Release|Win32
+		{2A7F483F-CD19-4F84-BBDA-B6A1865E2773}.Release|Win32.Build.0 = Release|Win32
 		{2A7F483F-CD19-4F84-BBDA-B6A1865E2773}.Release|x64.ActiveCfg = Release|x64
+		{2A7F483F-CD19-4F84-BBDA-B6A1865E2773}.Release|x64.Build.0 = Release|x64
 		{F67EB1EA-DCFA-4758-A2AA-4B570BA78036}.Debug|Win32.ActiveCfg = Debug|Win32
+		{F67EB1EA-DCFA-4758-A2AA-4B570BA78036}.Debug|Win32.Build.0 = Debug|Win32
 		{F67EB1EA-DCFA-4758-A2AA-4B570BA78036}.Debug|x64.ActiveCfg = Debug|x64
+		{F67EB1EA-DCFA-4758-A2AA-4B570BA78036}.Debug|x64.Build.0 = Debug|x64
 		{F67EB1EA-DCFA-4758-A2AA-4B570BA78036}.Release|Win32.ActiveCfg = Release|Win32
+		{F67EB1EA-DCFA-4758-A2AA-4B570BA78036}.Release|Win32.Build.0 = Release|Win32
 		{F67EB1EA-DCFA-4758-A2AA-4B570BA78036}.Release|x64.ActiveCfg = Release|x64
+		{F67EB1EA-DCFA-4758-A2AA-4B570BA78036}.Release|x64.Build.0 = Release|x64
 		{2C5AD347-6E34-463B-8289-00578E43B255}.Debug|Win32.ActiveCfg = Debug|Win32
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 		{2C5AD347-6E34-463B-8289-00578E43B255}.Debug|x64.ActiveCfg = Debug|x64
+		{2C5AD347-6E34-463B-8289-00578E43B255}.Debug|x64.Build.0 = Debug|x64
 		{2C5AD347-6E34-463B-8289-00578E43B255}.Release|Win32.ActiveCfg = Release|Win32
+		{2C5AD347-6E34-463B-8289-00578E43B255}.Release|Win32.Build.0 = Release|Win32
 		{2C5AD347-6E34-463B-8289-00578E43B255}.Release|x64.ActiveCfg = Release|x64
+		{2C5AD347-6E34-463B-8289-00578E43B255}.Release|x64.Build.0 = Release|x64
 		{63050112-E486-4396-B5E4-303C3BC12D39}.Debug|Win32.ActiveCfg = Debug|Win32
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 		{63050112-E486-4396-B5E4-303C3BC12D39}.Debug|x64.ActiveCfg = Debug|x64
+		{63050112-E486-4396-B5E4-303C3BC12D39}.Debug|x64.Build.0 = Debug|x64
 		{63050112-E486-4396-B5E4-303C3BC12D39}.Release|Win32.ActiveCfg = Release|Win32
+		{63050112-E486-4396-B5E4-303C3BC12D39}.Release|Win32.Build.0 = Release|Win32
 		{63050112-E486-4396-B5E4-303C3BC12D39}.Release|x64.ActiveCfg = Release|x64
+		{63050112-E486-4396-B5E4-303C3BC12D39}.Release|x64.Build.0 = Release|x64
 		{4A9F9353-DB63-460A-BB1C-9CB519DFD414}.Debug|Win32.ActiveCfg = Debug|Win32
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 		{4A9F9353-DB63-460A-BB1C-9CB519DFD414}.Debug|x64.ActiveCfg = Debug|x64
+		{4A9F9353-DB63-460A-BB1C-9CB519DFD414}.Debug|x64.Build.0 = Debug|x64
 		{4A9F9353-DB63-460A-BB1C-9CB519DFD414}.Release|Win32.ActiveCfg = Release|Win32
+		{4A9F9353-DB63-460A-BB1C-9CB519DFD414}.Release|Win32.Build.0 = Release|Win32
 		{4A9F9353-DB63-460A-BB1C-9CB519DFD414}.Release|x64.ActiveCfg = Release|x64
+		{4A9F9353-DB63-460A-BB1C-9CB519DFD414}.Release|x64.Build.0 = Release|x64
 		{4478909E-6983-425C-9D9F-558CF258E61E}.Debug|Win32.ActiveCfg = Debug|Win32
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 		{4478909E-6983-425C-9D9F-558CF258E61E}.Debug|x64.ActiveCfg = Debug|x64
+		{4478909E-6983-425C-9D9F-558CF258E61E}.Debug|x64.Build.0 = Debug|x64
 		{4478909E-6983-425C-9D9F-558CF258E61E}.Release|Win32.ActiveCfg = Release|Win32
+		{4478909E-6983-425C-9D9F-558CF258E61E}.Release|Win32.Build.0 = Release|Win32
 		{4478909E-6983-425C-9D9F-558CF258E61E}.Release|x64.ActiveCfg = Release|x64
+		{4478909E-6983-425C-9D9F-558CF258E61E}.Release|x64.Build.0 = Release|x64
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 		{006A7908-ABF3-4D18-BC35-0A29E39B95F9}.Debug|x64.ActiveCfg = Debug|x64
+		{006A7908-ABF3-4D18-BC35-0A29E39B95F9}.Debug|x64.Build.0 = Debug|x64
 		{006A7908-ABF3-4D18-BC35-0A29E39B95F9}.Release|Win32.ActiveCfg = Release|Win32
+		{006A7908-ABF3-4D18-BC35-0A29E39B95F9}.Release|Win32.Build.0 = Release|Win32
 		{006A7908-ABF3-4D18-BC35-0A29E39B95F9}.Release|x64.ActiveCfg = Release|x64
+		{006A7908-ABF3-4D18-BC35-0A29E39B95F9}.Release|x64.Build.0 = Release|x64
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 		{698C2D54-475C-446F-B879-F629BBEF75FE}.Debug|x64.ActiveCfg = Debug|x64
+		{698C2D54-475C-446F-B879-F629BBEF75FE}.Debug|x64.Build.0 = Debug|x64
 		{698C2D54-475C-446F-B879-F629BBEF75FE}.Release|Win32.ActiveCfg = Release|Win32
+		{698C2D54-475C-446F-B879-F629BBEF75FE}.Release|Win32.Build.0 = Release|Win32
 		{698C2D54-475C-446F-B879-F629BBEF75FE}.Release|x64.ActiveCfg = Release|x64
+		{698C2D54-475C-446F-B879-F629BBEF75FE}.Release|x64.Build.0 = Release|x64
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 		{8804AD29-E398-480C-AC0F-98EC1B7A51CB}.Debug|x64.ActiveCfg = Debug|x64
+		{8804AD29-E398-480C-AC0F-98EC1B7A51CB}.Debug|x64.Build.0 = Debug|x64
 		{8804AD29-E398-480C-AC0F-98EC1B7A51CB}.Release|Win32.ActiveCfg = Release|Win32
+		{8804AD29-E398-480C-AC0F-98EC1B7A51CB}.Release|Win32.Build.0 = Release|Win32
 		{8804AD29-E398-480C-AC0F-98EC1B7A51CB}.Release|x64.ActiveCfg = Release|x64
+		{8804AD29-E398-480C-AC0F-98EC1B7A51CB}.Release|x64.Build.0 = Release|x64
 		{9F32C692-9106-43AF-A291-779A2D8BE096}.Debug|Win32.ActiveCfg = Debug|Win32
 		{9F32C692-9106-43AF-A291-779A2D8BE096}.Debug|Win32.Build.0 = Debug|Win32
 		{9F32C692-9106-43AF-A291-779A2D8BE096}.Debug|x64.ActiveCfg = Debug|x64
+		{9F32C692-9106-43AF-A291-779A2D8BE096}.Debug|x64.Build.0 = Debug|x64
 		{9F32C692-9106-43AF-A291-779A2D8BE096}.Release|Win32.ActiveCfg = Release|Win32
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 		{9F32C692-9106-43AF-A291-779A2D8BE096}.Release|x64.ActiveCfg = Release|x64
+		{9F32C692-9106-43AF-A291-779A2D8BE096}.Release|x64.Build.0 = Release|x64
 		{9D588288-5A28-4AB3-96EA-442CAA508F8E}.Debug|Win32.ActiveCfg = Debug|Win32
 		{9D588288-5A28-4AB3-96EA-442CAA508F8E}.Debug|Win32.Build.0 = Debug|Win32
 		{9D588288-5A28-4AB3-96EA-442CAA508F8E}.Debug|x64.ActiveCfg = Debug|x64
+		{9D588288-5A28-4AB3-96EA-442CAA508F8E}.Debug|x64.Build.0 = Debug|x64
 		{9D588288-5A28-4AB3-96EA-442CAA508F8E}.Release|Win32.ActiveCfg = Release|Win32
 		{9D588288-5A28-4AB3-96EA-442CAA508F8E}.Release|Win32.Build.0 = Release|Win32
 		{9D588288-5A28-4AB3-96EA-442CAA508F8E}.Release|x64.ActiveCfg = Release|x64
+		{9D588288-5A28-4AB3-96EA-442CAA508F8E}.Release|x64.Build.0 = Release|x64
 		{04DC0E3A-F247-45C2-AE27-8DE7493AA43B}.Debug|Win32.ActiveCfg = Debug|Win32
 		{04DC0E3A-F247-45C2-AE27-8DE7493AA43B}.Debug|Win32.Build.0 = Debug|Win32
 		{04DC0E3A-F247-45C2-AE27-8DE7493AA43B}.Debug|x64.ActiveCfg = Debug|x64
@@ -183,42 +216,55 @@ Global
 		{04DC0E3A-F247-45C2-AE27-8DE7493AA43B}.Release|Win32.ActiveCfg = Release|Win32
 		{04DC0E3A-F247-45C2-AE27-8DE7493AA43B}.Release|Win32.Build.0 = Release|Win32
 		{04DC0E3A-F247-45C2-AE27-8DE7493AA43B}.Release|x64.ActiveCfg = Release|x64
+		{04DC0E3A-F247-45C2-AE27-8DE7493AA43B}.Release|x64.Build.0 = Release|x64
 		{7AA02EDF-D797-494B-929C-F628F4E4EA62}.Debug|Win32.ActiveCfg = Debug|Win32
 		{7AA02EDF-D797-494B-929C-F628F4E4EA62}.Debug|Win32.Build.0 = Debug|Win32
 		{7AA02EDF-D797-494B-929C-F628F4E4EA62}.Debug|x64.ActiveCfg = Debug|x64
+		{7AA02EDF-D797-494B-929C-F628F4E4EA62}.Debug|x64.Build.0 = Debug|x64
 		{7AA02EDF-D797-494B-929C-F628F4E4EA62}.Release|Win32.ActiveCfg = Release|Win32
 		{7AA02EDF-D797-494B-929C-F628F4E4EA62}.Release|Win32.Build.0 = Release|Win32
 		{7AA02EDF-D797-494B-929C-F628F4E4EA62}.Release|x64.ActiveCfg = Release|x64
+		{7AA02EDF-D797-494B-929C-F628F4E4EA62}.Release|x64.Build.0 = Release|x64
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 		{11727C54-463F-472A-88AF-6C3D6071BF0B}.Debug|x64.ActiveCfg = Debug|x64
+		{11727C54-463F-472A-88AF-6C3D6071BF0B}.Debug|x64.Build.0 = Debug|x64
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 		{11727C54-463F-472A-88AF-6C3D6071BF0B}.Release|x64.ActiveCfg = Release|x64
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 		{E34ECD90-3977-4A4B-9641-4D7F1766E9FD}.Release|x64.ActiveCfg = Release|x64
+		{E34ECD90-3977-4A4B-9641-4D7F1766E9FD}.Release|x64.Build.0 = Release|x64
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 		{A25CA34D-2F64-442B-A5D3-B13CB56C9957}.Debug|x64.ActiveCfg = Debug|x64
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 	EndGlobalSection
 	GlobalSection(SolutionProperties) = preSolution
 		HideSolutionNode = FALSE

msvc/unicorn/aarch64-softmmu/aarch64-softmmu.vcxproj

@@ -19,8 +19,62 @@
     </ProjectConfiguration>
   </ItemGroup>
   <ItemGroup>
+    <ClInclude Include="..\..\..\qemu\aarch64.h" />
+    <ClInclude Include="..\..\..\qemu\fpu\softfloat-macros.h" />
+    <ClInclude Include="..\..\..\qemu\fpu\softfloat-specialize.h" />
+    <ClInclude Include="..\..\..\qemu\target-arm\arm_ldst.h" />
+    <ClInclude Include="..\..\..\qemu\target-arm\cpu-qom.h" />
+    <ClInclude Include="..\..\..\qemu\target-arm\cpu.h" />
+    <ClInclude Include="..\..\..\qemu\target-arm\helper-a64.h" />
+    <ClInclude Include="..\..\..\qemu\target-arm\helper.h" />
+    <ClInclude Include="..\..\..\qemu\target-arm\internals.h" />
+    <ClInclude Include="..\..\..\qemu\target-arm\kvm-consts.h" />
+    <ClInclude Include="..\..\..\qemu\target-arm\op_addsub.h" />
+    <ClInclude Include="..\..\..\qemu\target-arm\translate.h" />
+    <ClInclude Include="..\..\..\qemu\target-arm\unicorn.h" />
+    <ClInclude Include="..\..\..\qemu\tcg\i386\tcg-target.h" />
+    <ClInclude Include="..\..\..\qemu\tcg\tcg-be-ldst.h" />
+    <ClInclude Include="..\..\..\qemu\tcg\tcg-be-null.h" />
+    <ClInclude Include="..\..\..\qemu\tcg\tcg-op.h" />
+    <ClInclude Include="..\..\..\qemu\tcg\tcg-opc.h" />
+    <ClInclude Include="..\..\..\qemu\tcg\tcg-runtime.h" />
+    <ClInclude Include="..\..\..\qemu\tcg\tcg.h" />
+    <ClInclude Include="..\config-host.h" />
     <ClInclude Include="config-target.h" />
   </ItemGroup>
+  <ItemGroup>
+    <ClCompile Include="..\..\..\qemu\cpu-exec.c" />
+    <ClCompile Include="..\..\..\qemu\cpus.c" />
+    <ClCompile Include="..\..\..\qemu\cputlb.c" />
+    <ClCompile Include="..\..\..\qemu\exec.c" />
+    <ClCompile Include="..\..\..\qemu\fpu\softfloat.c" />
+    <ClCompile Include="..\..\..\qemu\hw\arm\tosa.c" />
+    <ClCompile Include="..\..\..\qemu\hw\arm\virt.c" />
+    <ClCompile Include="..\..\..\qemu\ioport.c" />
+    <ClCompile Include="..\..\..\qemu\memory.c" />
+    <ClCompile Include="..\..\..\qemu\memory_mapping.c" />
+    <ClCompile Include="..\..\..\qemu\target-arm\cpu.c" />
+    <ClCompile Include="..\..\..\qemu\target-arm\cpu64.c" />
+    <ClCompile Include="..\..\..\qemu\target-arm\crypto_helper.c" />
+    <ClCompile Include="..\..\..\qemu\target-arm\helper-a64.c" />
+    <ClCompile Include="..\..\..\qemu\target-arm\helper.c" />
+    <ClCompile Include="..\..\..\qemu\target-arm\iwmmxt_helper.c" />
+    <ClCompile Include="..\..\..\qemu\target-arm\neon_helper.c" />
+    <ClCompile Include="..\..\..\qemu\target-arm\op_helper.c" />
+    <ClCompile Include="..\..\..\qemu\target-arm\psci.c" />
+    <ClCompile Include="..\..\..\qemu\target-arm\translate-a64.c" />
+    <ClCompile Include="..\..\..\qemu\target-arm\translate.c" />
+    <ClCompile Include="..\..\..\qemu\target-arm\unicorn_aarch64.c" />
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+    </ClCompile>
+    <ClCompile Include="..\..\..\qemu\tcg\optimize.c" />
+    <ClCompile Include="..\..\..\qemu\tcg\tcg.c" />
+    <ClCompile Include="..\..\..\qemu\translate-all.c" />
+  </ItemGroup>
   <PropertyGroup Label="Globals">
     <ProjectGuid>{2A7F483F-CD19-4F84-BBDA-B6A1865E2773}</ProjectGuid>
     <Keyword>Win32Proj</Keyword>

msvc/unicorn/aarch64-softmmu/aarch64-softmmu.vcxproj.filters

@@ -2,5 +2,148 @@
 <Project ToolsVersion="4.0" xmlns="http://schemas.microsoft.com/developer/msbuild/2003">
   <ItemGroup>
     <ClInclude Include="config-target.h" />
+    <ClInclude Include="..\config-host.h" />
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+      <Filter>fpu</Filter>
+    </ClInclude>
+    <ClInclude Include="..\..\..\qemu\fpu\softfloat-specialize.h">
+      <Filter>fpu</Filter>
+    </ClInclude>
+    <ClInclude Include="..\..\..\qemu\tcg\tcg-be-ldst.h">
+      <Filter>tcg</Filter>
+    </ClInclude>
+    <ClInclude Include="..\..\..\qemu\tcg\tcg-be-null.h">
+      <Filter>tcg</Filter>
+    </ClInclude>
+    <ClInclude Include="..\..\..\qemu\tcg\tcg-op.h">
+      <Filter>tcg</Filter>
+    </ClInclude>
+    <ClInclude Include="..\..\..\qemu\tcg\tcg-opc.h">
+      <Filter>tcg</Filter>
+    </ClInclude>
+    <ClInclude Include="..\..\..\qemu\tcg\tcg-runtime.h">
+      <Filter>tcg</Filter>
+    </ClInclude>
+    <ClInclude Include="..\..\..\qemu\tcg\tcg.h">
+      <Filter>tcg</Filter>
+    </ClInclude>
+    <ClInclude Include="..\..\..\qemu\tcg\i386\tcg-target.h">
+      <Filter>tcg\i386</Filter>
+    </ClInclude>
+    <ClInclude Include="..\..\..\qemu\aarch64.h" />
+    <ClInclude Include="..\..\..\qemu\target-arm\arm_ldst.h">
+      <Filter>target-arm</Filter>
+    </ClInclude>
+    <ClInclude Include="..\..\..\qemu\target-arm\cpu.h">
+      <Filter>target-arm</Filter>
+    </ClInclude>
+    <ClInclude Include="..\..\..\qemu\target-arm\cpu-qom.h">
+      <Filter>target-arm</Filter>
+    </ClInclude>
+    <ClInclude Include="..\..\..\qemu\target-arm\helper.h">
+      <Filter>target-arm</Filter>
+    </ClInclude>
+    <ClInclude Include="..\..\..\qemu\target-arm\internals.h">
+      <Filter>target-arm</Filter>
+    </ClInclude>
+    <ClInclude Include="..\..\..\qemu\target-arm\kvm-consts.h">
+      <Filter>target-arm</Filter>
+    </ClInclude>
+    <ClInclude Include="..\..\..\qemu\target-arm\op_addsub.h">
+      <Filter>target-arm</Filter>
+    </ClInclude>
+    <ClInclude Include="..\..\..\qemu\target-arm\translate.h">
+      <Filter>target-arm</Filter>
+    </ClInclude>
+    <ClInclude Include="..\..\..\qemu\target-arm\unicorn.h">
+      <Filter>target-arm</Filter>
+    </ClInclude>
+    <ClInclude Include="..\..\..\qemu\target-arm\helper-a64.h">
+      <Filter>target-arm</Filter>
+    </ClInclude>
+  </ItemGroup>
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+    <ClCompile Include="..\..\..\qemu\cputlb.c" />
+    <ClCompile Include="..\..\..\qemu\exec.c" />
+    <ClCompile Include="..\..\..\qemu\ioport.c" />
+    <ClCompile Include="..\..\..\qemu\memory.c" />
+    <ClCompile Include="..\..\..\qemu\memory_mapping.c" />
+    <ClCompile Include="..\..\..\qemu\translate-all.c" />
+    <ClCompile Include="..\..\..\qemu\fpu\softfloat.c">
+      <Filter>fpu</Filter>
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+    <ClCompile Include="..\..\..\qemu\tcg\optimize.c">
+      <Filter>tcg</Filter>
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+      <Filter>tcg</Filter>
+    </ClCompile>
+    <ClCompile Include="..\..\..\qemu\tcg\i386\tcg-target.c">
+      <Filter>tcg\i386</Filter>
+    </ClCompile>
+    <ClCompile Include="..\..\..\qemu\hw\arm\tosa.c">
+      <Filter>hw\arm</Filter>
+    </ClCompile>
+    <ClCompile Include="..\..\..\qemu\hw\arm\virt.c">
+      <Filter>hw\arm</Filter>
+    </ClCompile>
+    <ClCompile Include="..\..\..\qemu\target-arm\cpu.c">
+      <Filter>target-arm</Filter>
+    </ClCompile>
+    <ClCompile Include="..\..\..\qemu\target-arm\crypto_helper.c">
+      <Filter>target-arm</Filter>
+    </ClCompile>
+    <ClCompile Include="..\..\..\qemu\target-arm\helper.c">
+      <Filter>target-arm</Filter>
+    </ClCompile>
+    <ClCompile Include="..\..\..\qemu\target-arm\iwmmxt_helper.c">
+      <Filter>target-arm</Filter>
+    </ClCompile>
+    <ClCompile Include="..\..\..\qemu\target-arm\neon_helper.c">
+      <Filter>target-arm</Filter>
+    </ClCompile>
+    <ClCompile Include="..\..\..\qemu\target-arm\op_helper.c">
+      <Filter>target-arm</Filter>
+    </ClCompile>
+    <ClCompile Include="..\..\..\qemu\target-arm\psci.c">
+      <Filter>target-arm</Filter>
+    </ClCompile>
+    <ClCompile Include="..\..\..\qemu\target-arm\translate.c">
+      <Filter>target-arm</Filter>
+    </ClCompile>
+    <ClCompile Include="..\..\..\qemu\target-arm\unicorn_aarch64.c">
+      <Filter>target-arm</Filter>
+    </ClCompile>
+    <ClCompile Include="..\..\..\qemu\target-arm\cpu64.c">
+      <Filter>target-arm</Filter>
+    </ClCompile>
+    <ClCompile Include="..\..\..\qemu\target-arm\helper-a64.c">
+      <Filter>target-arm</Filter>
+    </ClCompile>
+    <ClCompile Include="..\..\..\qemu\target-arm\translate-a64.c">
+      <Filter>target-arm</Filter>
+    </ClCompile>
+  </ItemGroup>
+  <ItemGroup>
+    <Filter Include="fpu">
+      <UniqueIdentifier>{8a7d2815-3656-4ae7-8eb2-d38da6e8d480}</UniqueIdentifier>
+    </Filter>
+    <Filter Include="tcg">
+      <UniqueIdentifier>{ca50b33c-f5ce-4975-a702-c607bb2fc604}</UniqueIdentifier>
+    </Filter>
+    <Filter Include="tcg\i386">
+      <UniqueIdentifier>{1db81436-53cf-4cb6-a474-e76327883bd2}</UniqueIdentifier>
+    </Filter>
+    <Filter Include="hw">
+      <UniqueIdentifier>{9a7f2b42-3f31-4731-84e2-38f535304a1d}</UniqueIdentifier>
+    </Filter>
+    <Filter Include="hw\arm">
+      <UniqueIdentifier>{c74d3c4d-1f19-42c6-bf25-26820a53ac11}</UniqueIdentifier>
+    </Filter>
+    <Filter Include="target-arm">
+      <UniqueIdentifier>{0e231806-86e4-4e05-8ef8-3e3d36860b00}</UniqueIdentifier>
+    </Filter>
   </ItemGroup>
 </Project>

msvc/unicorn/arm-softmmu/arm-softmmu.vcxproj

@@ -19,8 +19,58 @@
     </ProjectConfiguration>
   </ItemGroup>
   <ItemGroup>
+    <ClInclude Include="..\..\..\qemu\arm.h" />
+    <ClInclude Include="..\..\..\qemu\fpu\softfloat-macros.h" />
+    <ClInclude Include="..\..\..\qemu\fpu\softfloat-specialize.h" />
+    <ClInclude Include="..\..\..\qemu\target-arm\arm_ldst.h" />
+    <ClInclude Include="..\..\..\qemu\target-arm\cpu-qom.h" />
+    <ClInclude Include="..\..\..\qemu\target-arm\cpu.h" />
+    <ClInclude Include="..\..\..\qemu\target-arm\helper.h" />
+    <ClInclude Include="..\..\..\qemu\target-arm\internals.h" />
+    <ClInclude Include="..\..\..\qemu\target-arm\kvm-consts.h" />
+    <ClInclude Include="..\..\..\qemu\target-arm\op_addsub.h" />
+    <ClInclude Include="..\..\..\qemu\target-arm\translate.h" />
+    <ClInclude Include="..\..\..\qemu\target-arm\unicorn.h" />
+    <ClInclude Include="..\..\..\qemu\tcg\i386\tcg-target.h" />
+    <ClInclude Include="..\..\..\qemu\tcg\tcg-be-ldst.h" />
+    <ClInclude Include="..\..\..\qemu\tcg\tcg-be-null.h" />
+    <ClInclude Include="..\..\..\qemu\tcg\tcg-op.h" />
+    <ClInclude Include="..\..\..\qemu\tcg\tcg-opc.h" />
+    <ClInclude Include="..\..\..\qemu\tcg\tcg-runtime.h" />
+    <ClInclude Include="..\..\..\qemu\tcg\tcg.h" />
+    <ClInclude Include="..\config-host.h" />
     <ClInclude Include="config-target.h" />
   </ItemGroup>
+  <ItemGroup>
+    <ClCompile Include="..\..\..\qemu\cpu-exec.c" />
+    <ClCompile Include="..\..\..\qemu\cpus.c" />
+    <ClCompile Include="..\..\..\qemu\cputlb.c" />
+    <ClCompile Include="..\..\..\qemu\exec.c" />
+    <ClCompile Include="..\..\..\qemu\fpu\softfloat.c" />
+    <ClCompile Include="..\..\..\qemu\hw\arm\tosa.c" />
+    <ClCompile Include="..\..\..\qemu\hw\arm\virt.c" />
+    <ClCompile Include="..\..\..\qemu\ioport.c" />
+    <ClCompile Include="..\..\..\qemu\memory.c" />
+    <ClCompile Include="..\..\..\qemu\memory_mapping.c" />
+    <ClCompile Include="..\..\..\qemu\target-arm\cpu.c" />
+    <ClCompile Include="..\..\..\qemu\target-arm\crypto_helper.c" />
+    <ClCompile Include="..\..\..\qemu\target-arm\helper.c" />
+    <ClCompile Include="..\..\..\qemu\target-arm\iwmmxt_helper.c" />
+    <ClCompile Include="..\..\..\qemu\target-arm\neon_helper.c" />
+    <ClCompile Include="..\..\..\qemu\target-arm\op_helper.c" />
+    <ClCompile Include="..\..\..\qemu\target-arm\psci.c" />
+    <ClCompile Include="..\..\..\qemu\target-arm\translate.c" />
+    <ClCompile Include="..\..\..\qemu\target-arm\unicorn_arm.c" />
+    <ClCompile Include="..\..\..\qemu\tcg\i386\tcg-target.c">
+      <ExcludedFromBuild Condition="'$(Configuration)|$(Platform)'=='Debug|Win32'">true</ExcludedFromBuild>
+      <ExcludedFromBuild Condition="'$(Configuration)|$(Platform)'=='Release|Win32'">true</ExcludedFromBuild>
+      <ExcludedFromBuild Condition="'$(Configuration)|$(Platform)'=='Debug|x64'">true</ExcludedFromBuild>
+      <ExcludedFromBuild Condition="'$(Configuration)|$(Platform)'=='Release|x64'">true</ExcludedFromBuild>
+    </ClCompile>
+    <ClCompile Include="..\..\..\qemu\tcg\optimize.c" />
+    <ClCompile Include="..\..\..\qemu\tcg\tcg.c" />
+    <ClCompile Include="..\..\..\qemu\translate-all.c" />
+  </ItemGroup>
   <PropertyGroup Label="Globals">
     <ProjectGuid>{F67EB1EA-DCFA-4758-A2AA-4B570BA78036}</ProjectGuid>
     <Keyword>Win32Proj</Keyword>

msvc/unicorn/arm-softmmu/arm-softmmu.vcxproj.filters

@@ -2,5 +2,136 @@
 <Project ToolsVersion="4.0" xmlns="http://schemas.microsoft.com/developer/msbuild/2003">
   <ItemGroup>
     <ClInclude Include="config-target.h" />
+    <ClInclude Include="..\config-host.h" />
+    <ClInclude Include="..\..\..\qemu\fpu\softfloat-macros.h">
+      <Filter>fpu</Filter>
+    </ClInclude>
+    <ClInclude Include="..\..\..\qemu\fpu\softfloat-specialize.h">
+      <Filter>fpu</Filter>
+    </ClInclude>
+    <ClInclude Include="..\..\..\qemu\tcg\tcg-be-ldst.h">
+      <Filter>tcg</Filter>
+    </ClInclude>
+    <ClInclude Include="..\..\..\qemu\tcg\tcg-be-null.h">
+      <Filter>tcg</Filter>
+    </ClInclude>
+    <ClInclude Include="..\..\..\qemu\tcg\tcg-op.h">
+      <Filter>tcg</Filter>
+    </ClInclude>
+    <ClInclude Include="..\..\..\qemu\tcg\tcg-opc.h">
+      <Filter>tcg</Filter>
+    </ClInclude>
+    <ClInclude Include="..\..\..\qemu\tcg\tcg-runtime.h">
+      <Filter>tcg</Filter>
+    </ClInclude>
+    <ClInclude Include="..\..\..\qemu\tcg\tcg.h">
+      <Filter>tcg</Filter>
+    </ClInclude>
+    <ClInclude Include="..\..\..\qemu\tcg\i386\tcg-target.h">
+      <Filter>tcg\i386</Filter>
+    </ClInclude>
+    <ClInclude Include="..\..\..\qemu\arm.h" />
+    <ClInclude Include="..\..\..\qemu\target-arm\arm_ldst.h">
+      <Filter>target-arm</Filter>
+    </ClInclude>
+    <ClInclude Include="..\..\..\qemu\target-arm\cpu.h">
+      <Filter>target-arm</Filter>
+    </ClInclude>
+    <ClInclude Include="..\..\..\qemu\target-arm\cpu-qom.h">
+      <Filter>target-arm</Filter>
+    </ClInclude>
+    <ClInclude Include="..\..\..\qemu\target-arm\helper.h">
+      <Filter>target-arm</Filter>
+    </ClInclude>
+    <ClInclude Include="..\..\..\qemu\target-arm\internals.h">
+      <Filter>target-arm</Filter>
+    </ClInclude>
+    <ClInclude Include="..\..\..\qemu\target-arm\kvm-consts.h">
+      <Filter>target-arm</Filter>
+    </ClInclude>
+    <ClInclude Include="..\..\..\qemu\target-arm\op_addsub.h">
+      <Filter>target-arm</Filter>
+    </ClInclude>
+    <ClInclude Include="..\..\..\qemu\target-arm\translate.h">
+      <Filter>target-arm</Filter>
+    </ClInclude>
+    <ClInclude Include="..\..\..\qemu\target-arm\unicorn.h">
+      <Filter>target-arm</Filter>
+    </ClInclude>
+  </ItemGroup>
+  <ItemGroup>
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+    <ClCompile Include="..\..\..\qemu\cpus.c" />
+    <ClCompile Include="..\..\..\qemu\cputlb.c" />
+    <ClCompile Include="..\..\..\qemu\exec.c" />
+    <ClCompile Include="..\..\..\qemu\ioport.c" />
+    <ClCompile Include="..\..\..\qemu\memory.c" />
+    <ClCompile Include="..\..\..\qemu\memory_mapping.c" />
+    <ClCompile Include="..\..\..\qemu\translate-all.c" />
+    <ClCompile Include="..\..\..\qemu\fpu\softfloat.c">
+      <Filter>fpu</Filter>
+    </ClCompile>
+    <ClCompile Include="..\..\..\qemu\tcg\optimize.c">
+      <Filter>tcg</Filter>
+    </ClCompile>
+    <ClCompile Include="..\..\..\qemu\tcg\tcg.c">
+      <Filter>tcg</Filter>
+    </ClCompile>
+    <ClCompile Include="..\..\..\qemu\tcg\i386\tcg-target.c">
+      <Filter>tcg\i386</Filter>
+    </ClCompile>
+    <ClCompile Include="..\..\..\qemu\hw\arm\tosa.c">
+      <Filter>hw\arm</Filter>
+    </ClCompile>
+    <ClCompile Include="..\..\..\qemu\hw\arm\virt.c">
+      <Filter>hw\arm</Filter>
+    </ClCompile>
+    <ClCompile Include="..\..\..\qemu\target-arm\translate.c">
+      <Filter>target-arm</Filter>
+    </ClCompile>
+    <ClCompile Include="..\..\..\qemu\target-arm\cpu.c">
+      <Filter>target-arm</Filter>
+    </ClCompile>
+    <ClCompile Include="..\..\..\qemu\target-arm\crypto_helper.c">
+      <Filter>target-arm</Filter>
+    </ClCompile>
+    <ClCompile Include="..\..\..\qemu\target-arm\helper.c">
+      <Filter>target-arm</Filter>
+    </ClCompile>
+    <ClCompile Include="..\..\..\qemu\target-arm\iwmmxt_helper.c">
+      <Filter>target-arm</Filter>
+    </ClCompile>
+    <ClCompile Include="..\..\..\qemu\target-arm\neon_helper.c">
+      <Filter>target-arm</Filter>
+    </ClCompile>
+    <ClCompile Include="..\..\..\qemu\target-arm\op_helper.c">
+      <Filter>target-arm</Filter>
+    </ClCompile>
+    <ClCompile Include="..\..\..\qemu\target-arm\psci.c">
+      <Filter>target-arm</Filter>
+    </ClCompile>
+    <ClCompile Include="..\..\..\qemu\target-arm\unicorn_arm.c">
+      <Filter>target-arm</Filter>
+    </ClCompile>
+  </ItemGroup>
+  <ItemGroup>
+    <Filter Include="fpu">
+      <UniqueIdentifier>{c29e2ed5-3ecd-426d-9245-04de2c8ce754}</UniqueIdentifier>
+    </Filter>
+    <Filter Include="tcg">
+      <UniqueIdentifier>{a9187bf5-cd27-47c7-8add-55b11a1150a9}</UniqueIdentifier>
+    </Filter>
+    <Filter Include="tcg\i386">
+      <UniqueIdentifier>{015b3e43-eb63-4add-9f53-f3ac3033472f}</UniqueIdentifier>
+    </Filter>
+    <Filter Include="hw">
+      <UniqueIdentifier>{89b122b1-9e4c-41b1-8670-c6d9ee3716f6}</UniqueIdentifier>
+    </Filter>
+    <Filter Include="hw\arm">
+      <UniqueIdentifier>{76f837ed-af45-43bf-9ee7-193dbdec1cd5}</UniqueIdentifier>
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   </ItemGroup>
 </Project>

msvc/unicorn/unicorn/unicorn.vcxproj

@@ -237,7 +237,7 @@
       </PrecompiledHeader>
       <WarningLevel>Level3</WarningLevel>
       <Optimization>Disabled</Optimization>
-      <PreprocessorDefinitions>WIN32;_DEBUG;_LIB;%(PreprocessorDefinitions);_CRT_SECURE_NO_WARNINGS;inline=__inline;__func__=__FUNCTION__;__i386__;UNICORN_HAS_M68K;UNICORN_HAS_MIPS;UNICORN_HAS_MIPS64;UNICORN_HAS_MIPSEL;UNICORN_HAS_MIPS64EL;UNICORN_HAS_SPARC;UNICORN_HAS_X86</PreprocessorDefinitions>
+      <PreprocessorDefinitions>WIN32;_DEBUG;_LIB;%(PreprocessorDefinitions);_CRT_SECURE_NO_WARNINGS;inline=__inline;__func__=__FUNCTION__;__i386__;UNICORN_HAS_ARM;UNICORN_HAS_ARM64;UNICORN_HAS_M68K;UNICORN_HAS_MIPS;UNICORN_HAS_MIPS64;UNICORN_HAS_MIPSEL;UNICORN_HAS_MIPS64EL;UNICORN_HAS_SPARC;UNICORN_HAS_X86</PreprocessorDefinitions>
       <RuntimeLibrary>MultiThreadedDebug</RuntimeLibrary>
       <AdditionalIncludeDirectories>.;..;../../../include;../../../qemu;../../../qemu/include;../../../qemu/tcg</AdditionalIncludeDirectories>
       <AdditionalOptions>/wd4018 /wd4244 /wd4267 %(AdditionalOptions)</AdditionalOptions>
@@ -249,7 +249,7 @@
     </Link>
     <Lib>
       <AdditionalLibraryDirectories>$(SolutionDir)$(Platform)\$(Configuration)\</AdditionalLibraryDirectories>
-      <AdditionalDependencies>ws2_32.lib;m68k-softmmu.lib;mips-softmmu.lib;mips64-softmmu.lib;mipsel-softmmu.lib;mips64el-softmmu.lib;sparc-softmmu.lib;sparc64-softmmu.lib;x86_64-softmmu.lib</AdditionalDependencies>
+      <AdditionalDependencies>ws2_32.lib;aarch64-softmmu.lib;arm-softmmu.lib;m68k-softmmu.lib;mips-softmmu.lib;mips64-softmmu.lib;mipsel-softmmu.lib;mips64el-softmmu.lib;sparc-softmmu.lib;sparc64-softmmu.lib;x86_64-softmmu.lib</AdditionalDependencies>
     </Lib>
     <PreBuildEvent>
       <Command>..\prebuild_script.bat</Command>
@@ -261,7 +261,7 @@
       </PrecompiledHeader>
       <WarningLevel>Level3</WarningLevel>
       <Optimization>Disabled</Optimization>
-      <PreprocessorDefinitions>WIN32;_DEBUG;_LIB;%(PreprocessorDefinitions);_CRT_SECURE_NO_WARNINGS;inline=__inline;__func__=__FUNCTION__;__x86_64__;UNICORN_HAS_M68K;UNICORN_HAS_MIPS;UNICORN_HAS_MIPS64;UNICORN_HAS_MIPSEL;UNICORN_HAS_MIPS64EL;UNICORN_HAS_SPARC;UNICORN_HAS_X86</PreprocessorDefinitions>
+      <PreprocessorDefinitions>WIN32;_DEBUG;_LIB;%(PreprocessorDefinitions);_CRT_SECURE_NO_WARNINGS;inline=__inline;__func__=__FUNCTION__;__x86_64__;UNICORN_HAS_ARM;UNICORN_HAS_ARM64;UNICORN_HAS_M68K;UNICORN_HAS_MIPS;UNICORN_HAS_MIPS64;UNICORN_HAS_MIPSEL;UNICORN_HAS_MIPS64EL;UNICORN_HAS_SPARC;UNICORN_HAS_X86</PreprocessorDefinitions>
       <RuntimeLibrary>MultiThreadedDebug</RuntimeLibrary>
       <AdditionalIncludeDirectories>.;..;../../../include;../../../qemu;../../../qemu/include;../../../qemu/tcg</AdditionalIncludeDirectories>
       <AdditionalOptions>/wd4018 /wd4244 /wd4267 %(AdditionalOptions)</AdditionalOptions>
@@ -273,7 +273,7 @@
     </Link>
     <Lib>
       <AdditionalLibraryDirectories>$(SolutionDir)$(Platform)\$(Configuration)\</AdditionalLibraryDirectories>
-      <AdditionalDependencies>ws2_32.lib;m68k-softmmu.lib;mips-softmmu.lib;mips64-softmmu.lib;mipsel-softmmu.lib;mips64el-softmmu.lib;sparc-softmmu.lib;sparc64-softmmu.lib;x86_64-softmmu.lib</AdditionalDependencies>
+      <AdditionalDependencies>ws2_32.lib;aarch64-softmmu.lib;arm-softmmu.lib;m68k-softmmu.lib;mips-softmmu.lib;mips64-softmmu.lib;mipsel-softmmu.lib;mips64el-softmmu.lib;sparc-softmmu.lib;sparc64-softmmu.lib;x86_64-softmmu.lib</AdditionalDependencies>
     </Lib>
     <PreBuildEvent>
       <Command>..\prebuild_script.bat</Command>
@@ -287,7 +287,7 @@
       <Optimization>MaxSpeed</Optimization>
       <FunctionLevelLinking>true</FunctionLevelLinking>
       <IntrinsicFunctions>true</IntrinsicFunctions>
-      <PreprocessorDefinitions>WIN32;NDEBUG;_LIB;%(PreprocessorDefinitions);_CRT_SECURE_NO_WARNINGS;inline=__inline;__func__=__FUNCTION__;__i386__;UNICORN_HAS_M68K;UNICORN_HAS_MIPS;UNICORN_HAS_MIPS64;UNICORN_HAS_MIPSEL;UNICORN_HAS_MIPS64EL;UNICORN_HAS_SPARC;UNICORN_HAS_X86</PreprocessorDefinitions>
+      <PreprocessorDefinitions>WIN32;NDEBUG;_LIB;%(PreprocessorDefinitions);_CRT_SECURE_NO_WARNINGS;inline=__inline;__func__=__FUNCTION__;__i386__;UNICORN_HAS_ARM;UNICORN_HAS_ARM64;UNICORN_HAS_M68K;UNICORN_HAS_MIPS;UNICORN_HAS_MIPS64;UNICORN_HAS_MIPSEL;UNICORN_HAS_MIPS64EL;UNICORN_HAS_SPARC;UNICORN_HAS_X86</PreprocessorDefinitions>
       <RuntimeLibrary>MultiThreaded</RuntimeLibrary>
       <AdditionalIncludeDirectories>.;..;../../../include;../../../qemu;../../../qemu/include;../../../qemu/tcg</AdditionalIncludeDirectories>
       <AdditionalOptions>/wd4018 /wd4244 /wd4267 %(AdditionalOptions)</AdditionalOptions>
@@ -301,7 +301,7 @@
     </Link>
     <Lib>
       <AdditionalLibraryDirectories>$(SolutionDir)$(Platform)\$(Configuration)\</AdditionalLibraryDirectories>
-      <AdditionalDependencies>ws2_32.lib;m68k-softmmu.lib;mips-softmmu.lib;mips64-softmmu.lib;mipsel-softmmu.lib;mips64el-softmmu.lib;sparc-softmmu.lib;sparc64-softmmu.lib;x86_64-softmmu.lib</AdditionalDependencies>
+      <AdditionalDependencies>ws2_32.lib;aarch64-softmmu.lib;arm-softmmu.lib;m68k-softmmu.lib;mips-softmmu.lib;mips64-softmmu.lib;mipsel-softmmu.lib;mips64el-softmmu.lib;sparc-softmmu.lib;sparc64-softmmu.lib;x86_64-softmmu.lib</AdditionalDependencies>
     </Lib>
     <PreBuildEvent>
       <Command>..\prebuild_script.bat</Command>
@@ -315,7 +315,7 @@
       <Optimization>MaxSpeed</Optimization>
       <FunctionLevelLinking>true</FunctionLevelLinking>
       <IntrinsicFunctions>true</IntrinsicFunctions>
-      <PreprocessorDefinitions>WIN32;NDEBUG;_LIB;%(PreprocessorDefinitions);_CRT_SECURE_NO_WARNINGS;inline=__inline;__func__=__FUNCTION__;__x86_64__;UNICORN_HAS_M68K;UNICORN_HAS_MIPS;UNICORN_HAS_MIPS64;UNICORN_HAS_MIPSEL;UNICORN_HAS_MIPS64EL;UNICORN_HAS_SPARC;UNICORN_HAS_X86</PreprocessorDefinitions>
+      <PreprocessorDefinitions>WIN32;NDEBUG;_LIB;%(PreprocessorDefinitions);_CRT_SECURE_NO_WARNINGS;inline=__inline;__func__=__FUNCTION__;__x86_64__;UNICORN_HAS_ARM;UNICORN_HAS_ARM64;UNICORN_HAS_M68K;UNICORN_HAS_MIPS;UNICORN_HAS_MIPS64;UNICORN_HAS_MIPSEL;UNICORN_HAS_MIPS64EL;UNICORN_HAS_SPARC;UNICORN_HAS_X86</PreprocessorDefinitions>
       <RuntimeLibrary>MultiThreaded</RuntimeLibrary>
       <AdditionalIncludeDirectories>.;..;../../../include;../../../qemu;../../../qemu/include;../../../qemu/tcg</AdditionalIncludeDirectories>
       <AdditionalOptions>/wd4018 /wd4244 /wd4267 %(AdditionalOptions)</AdditionalOptions>
@@ -329,7 +329,7 @@
     </Link>
     <Lib>
       <AdditionalLibraryDirectories>$(SolutionDir)$(Platform)\$(Configuration)\</AdditionalLibraryDirectories>
-      <AdditionalDependencies>ws2_32.lib;m68k-softmmu.lib;mips-softmmu.lib;mips64-softmmu.lib;mipsel-softmmu.lib;mips64el-softmmu.lib;sparc-softmmu.lib;sparc64-softmmu.lib;x86_64-softmmu.lib</AdditionalDependencies>
+      <AdditionalDependencies>ws2_32.lib;aarch64-softmmu.lib;arm-softmmu.lib;m68k-softmmu.lib;mips-softmmu.lib;mips64-softmmu.lib;mipsel-softmmu.lib;mips64el-softmmu.lib;sparc-softmmu.lib;sparc64-softmmu.lib;x86_64-softmmu.lib</AdditionalDependencies>
     </Lib>
     <PreBuildEvent>
       <Command>..\prebuild_script.bat</Command>

qemu/hw/arm/tosa.c

@@ -30,12 +30,11 @@ static int tosa_init(struct uc_struct *uc, MachineState *machine)
 
 void tosa_machine_init(struct uc_struct *uc)
 {
-    static QEMUMachine tosapda_machine = {
+    static QEMUMachine tosapda_machine = { 0 };
-        .name = "tosa",
+    tosapda_machine.name = "tosa",
-        .init = tosa_init,
+    tosapda_machine.init = tosa_init,
-        .is_default = 1,
+    tosapda_machine.is_default = 1,
-        .arch = UC_ARCH_ARM,
+    tosapda_machine.arch = UC_ARCH_ARM,
-    };
 
     qemu_register_machine(uc, &tosapda_machine, TYPE_MACHINE, NULL);
 }

qemu/hw/arm/virt.c

@@ -64,12 +64,11 @@ static int machvirt_init(struct uc_struct *uc, MachineState *machine)
 
 void machvirt_machine_init(struct uc_struct *uc)
 {
-    static QEMUMachine machvirt_a15_machine = {
+    static QEMUMachine machvirt_a15_machine = { 0 };
-        .name = "virt",
+    machvirt_a15_machine.name = "virt",
-        .init = machvirt_init,
+    machvirt_a15_machine.init = machvirt_init,
-        .is_default = 1,
+    machvirt_a15_machine.is_default = 1,
-        .arch = UC_ARCH_ARM64,
+    machvirt_a15_machine.arch = UC_ARCH_ARM64,
-    };
 
     qemu_register_machine(uc, &machvirt_a15_machine, TYPE_MACHINE, NULL);
 }

qemu/target-arm/cpu.c

@@ -469,12 +469,16 @@ static void arm1026_initfn(struct uc_struct *uc, Object *obj, void *opaque)
     cpu->reset_auxcr = 1;
     {
         /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
-        ARMCPRegInfo ifar = {
+        ARMCPRegInfo ifar = { 0 };
-            .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
+        ifar.name = "IFAR";
-            .access = PL1_RW,
+        ifar.cp = 15;
-            .fieldoffset = offsetofhigh32(CPUARMState, cp15.far_el[1]),
+        ifar.crn = 6;
-            .resetvalue = 0
+        ifar.crm = 0;
-        };
+        ifar.opc1 = 0;
+        ifar.opc2 = 1;
+        ifar.access = PL1_RW;
+        ifar.fieldoffset = offsetofhigh32(CPUARMState, cp15.far_el[1]);
+        ifar.resetvalue = 0;
         define_one_arm_cp_reg(cpu, &ifar);
     }
 }
@@ -631,10 +635,10 @@ static void arm_v7m_class_init(struct uc_struct *uc, ObjectClass *oc, void *data
 }
 
 static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
-    { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0,
+    { "L2LOCKDOWN", 15, 9, 0, 0,1,0, 0,
-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+      ARM_CP_CONST, PL1_RW,  NULL, 0, },
-    { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
+    { "L2AUXCR",    15, 9, 0, 0,1,2, 0,
-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+      ARM_CP_CONST, PL1_RW,  NULL, 0, },
     REGINFO_SENTINEL
 };
 
@@ -680,28 +684,28 @@ static const ARMCPRegInfo cortexa9_cp_reginfo[] = {
     /* power_control should be set to maximum latency. Again,
      * default to 0 and set by private hook
      */
-    { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
+    { "A9_PWRCTL", 15,15,0, 0,0,0, 0,
-      .access = PL1_RW, .resetvalue = 0,
+      0,            PL1_RW, NULL, 0,
-      .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) },
+      offsetof(CPUARMState, cp15.c15_power_control) },
-    { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1,
+    { "A9_DIAG",   15,15,0, 0,0,1, 0,
-      .access = PL1_RW, .resetvalue = 0,
+      0,            PL1_RW, NULL, 0,
-      .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) },
+      offsetof(CPUARMState, cp15.c15_diagnostic) },
-    { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2,
+    { "A9_PWRDIAG",15,15,0, 0,0,2, 0,
-      .access = PL1_RW, .resetvalue = 0,
+      0,            PL1_RW, NULL, 0,
-      .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) },
+      offsetof(CPUARMState, cp15.c15_power_diagnostic) },
-    { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
+    { "NEONBUSY",  15,15,1, 0,0,0, 0,
-      .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
+      ARM_CP_CONST, PL1_RW, NULL, 0,  },
     /* TLB lockdown control */
-    { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2,
+    { "TLB_LOCKR", 15,15,4, 0,5,2, 0,
-      .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
+      ARM_CP_NOP,   PL1_W,  NULL, 0 },
-    { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4,
+    { "TLB_LOCKW", 15,15,4, 0,5,4, 0,
-      .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
+      ARM_CP_NOP,   PL1_W,  NULL, 0, },
-    { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2,
+    { "TLB_VA",    15,15,5, 0,5,2, 0,
-      .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
+      ARM_CP_CONST, PL1_RW, NULL, 0,  },
-    { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2,
+    { "TLB_PA",    15,15,6, 0,5,2, 0,
-      .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
+      ARM_CP_CONST, PL1_RW, NULL, 0 },
-    { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2,
+    { "TLB_ATTR",  15,15,7, 0,5,2, 0,
-      .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
+      ARM_CP_CONST, PL1_RW, NULL, 0,  },
     REGINFO_SENTINEL
 };
 
@@ -759,12 +763,12 @@ static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
 
 static const ARMCPRegInfo cortexa15_cp_reginfo[] = {
 #ifndef CONFIG_USER_ONLY
-    { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
+    { "L2CTLR",  15,9,0, 0,1,2, 0,
-      .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read,
+      0,            PL1_RW, NULL, 0, 0, NULL, a15_l2ctlr_read,
-      .writefn = arm_cp_write_ignore, },
+      arm_cp_write_ignore, },
 #endif
-    { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3,
+    { "L2ECTLR", 15,9,0, 0,1,3, 0,
-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+      ARM_CP_CONST, PL1_RW, NULL, 0 },
     REGINFO_SENTINEL
 };
 
@@ -1005,43 +1009,42 @@ typedef struct ARMCPUInfo {
 
 static const ARMCPUInfo arm_cpus[] = {
 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
-    { .name = "arm926",      .initfn = arm926_initfn },
+    { "arm926",      arm926_initfn },
-    { .name = "arm946",      .initfn = arm946_initfn },
+    { "arm946",      arm946_initfn },
-    { .name = "arm1026",     .initfn = arm1026_initfn },
+    { "arm1026",     arm1026_initfn },
     /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
      * older core than plain "arm1136". In particular this does not
      * have the v6K features.
      */
-    { .name = "arm1136-r2",  .initfn = arm1136_r2_initfn },
+    { "arm1136-r2",  arm1136_r2_initfn },
-    { .name = "arm1136",     .initfn = arm1136_initfn },
+    { "arm1136",     arm1136_initfn },
-    { .name = "arm1176",     .initfn = arm1176_initfn },
+    { "arm1176",     arm1176_initfn },
-    { .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
+    { "arm11mpcore", arm11mpcore_initfn },
-    { .name = "cortex-m3",   .initfn = cortex_m3_initfn,
+    { "cortex-m3",   cortex_m3_initfn, arm_v7m_class_init },
-                             .class_init = arm_v7m_class_init },
+    { "cortex-a8",   cortex_a8_initfn },
-    { .name = "cortex-a8",   .initfn = cortex_a8_initfn },
+    { "cortex-a9",   cortex_a9_initfn },
-    { .name = "cortex-a9",   .initfn = cortex_a9_initfn },
+    { "cortex-a15",  cortex_a15_initfn },
-    { .name = "cortex-a15",  .initfn = cortex_a15_initfn },
+    { "ti925t",      ti925t_initfn },
-    { .name = "ti925t",      .initfn = ti925t_initfn },
+    { "sa1100",      sa1100_initfn },
-    { .name = "sa1100",      .initfn = sa1100_initfn },
+    { "sa1110",      sa1110_initfn },
-    { .name = "sa1110",      .initfn = sa1110_initfn },
+    { "pxa250",      pxa250_initfn },
-    { .name = "pxa250",      .initfn = pxa250_initfn },
+    { "pxa255",      pxa255_initfn },
-    { .name = "pxa255",      .initfn = pxa255_initfn },
+    { "pxa260",      pxa260_initfn },
-    { .name = "pxa260",      .initfn = pxa260_initfn },
+    { "pxa261",      pxa261_initfn },
-    { .name = "pxa261",      .initfn = pxa261_initfn },
+    { "pxa262",      pxa262_initfn },
-    { .name = "pxa262",      .initfn = pxa262_initfn },
     /* "pxa270" is an alias for "pxa270-a0" */
-    { .name = "pxa270",      .initfn = pxa270a0_initfn },
+    { "pxa270",      pxa270a0_initfn },
-    { .name = "pxa270-a0",   .initfn = pxa270a0_initfn },
+    { "pxa270-a0",   pxa270a0_initfn },
-    { .name = "pxa270-a1",   .initfn = pxa270a1_initfn },
+    { "pxa270-a1",   pxa270a1_initfn },
-    { .name = "pxa270-b0",   .initfn = pxa270b0_initfn },
+    { "pxa270-b0",   pxa270b0_initfn },
-    { .name = "pxa270-b1",   .initfn = pxa270b1_initfn },
+    { "pxa270-b1",   pxa270b1_initfn },
-    { .name = "pxa270-c0",   .initfn = pxa270c0_initfn },
+    { "pxa270-c0",   pxa270c0_initfn },
-    { .name = "pxa270-c5",   .initfn = pxa270c5_initfn },
+    { "pxa270-c5",   pxa270c5_initfn },
 #ifdef CONFIG_USER_ONLY
-    { .name = "any",         .initfn = arm_any_initfn },
+    { "any",         arm_any_initfn },
 #endif
 #endif
-    { .name = NULL }
+    { NULL }
 };
 
 static void arm_cpu_class_init(struct uc_struct *uc, ObjectClass *oc, void *data)
@@ -1073,13 +1076,12 @@ static void arm_cpu_class_init(struct uc_struct *uc, ObjectClass *oc, void *data
 
 static void cpu_register(struct uc_struct *uc, const ARMCPUInfo *info)
 {
-    TypeInfo type_info = {
+    TypeInfo type_info = { 0 };
-        .parent = TYPE_ARM_CPU,
+    type_info.parent = TYPE_ARM_CPU;
-        .instance_size = sizeof(ARMCPU),
+    type_info.instance_size = sizeof(ARMCPU);
-        .instance_init = info->initfn,
+    type_info.instance_init = info->initfn;
-        .class_size = sizeof(ARMCPUClass),
+    type_info.class_size = sizeof(ARMCPUClass);
-        .class_init = info->class_init,
+    type_info.class_init = info->class_init;
-    };
 
     type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
     type_register(uc, &type_info);
@@ -1088,21 +1090,20 @@ static void cpu_register(struct uc_struct *uc, const ARMCPUInfo *info)
 
 void arm_cpu_register_types(void *opaque)
 {
-    const TypeInfo arm_cpu_type_info = {
-        .name = TYPE_ARM_CPU,
-        .parent = TYPE_CPU,
-        .instance_userdata = opaque,
-        .instance_size = sizeof(ARMCPU),
-        .instance_init = arm_cpu_initfn,
-        .instance_post_init = arm_cpu_post_init,
-        .instance_finalize = arm_cpu_finalizefn,
-        .abstract = true,
-        .class_size = sizeof(ARMCPUClass),
-        .class_init = arm_cpu_class_init,
-    };
-
     const ARMCPUInfo *info = arm_cpus;
     
+    TypeInfo arm_cpu_type_info = { 0 };
+    arm_cpu_type_info.name = TYPE_ARM_CPU,
+    arm_cpu_type_info.parent = TYPE_CPU,
+    arm_cpu_type_info.instance_userdata = opaque,
+    arm_cpu_type_info.instance_size = sizeof(ARMCPU),
+    arm_cpu_type_info.instance_init = arm_cpu_initfn,
+    arm_cpu_type_info.instance_post_init = arm_cpu_post_init,
+    arm_cpu_type_info.instance_finalize = arm_cpu_finalizefn,
+    arm_cpu_type_info.abstract = true,
+    arm_cpu_type_info.class_size = sizeof(ARMCPUClass),
+    arm_cpu_type_info.class_init = arm_cpu_class_init,
+
     type_register_static(opaque, &arm_cpu_type_info);
 
     while (info->name) {

qemu/target-arm/cpu.h

@@ -1146,7 +1146,7 @@ struct ARMCPRegInfo {
 #define CPREG_FIELD64(env, ri) \
     (*(uint64_t *)((char *)(env) + (ri)->fieldoffset))
 
-#define REGINFO_SENTINEL { .type = ARM_CP_SENTINEL }
+#define REGINFO_SENTINEL { NULL, 0,0,0,0,0,0, 0, ARM_CP_SENTINEL, 0, NULL, 0,0,0,0,0,0,0,0, }
 
 void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
                                     const ARMCPRegInfo *regs, void *opaque);

qemu/target-arm/cpu64.c

@@ -38,48 +38,35 @@ static uint64_t a57_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
 
 static const ARMCPRegInfo cortexa57_cp_reginfo[] = {
 #ifndef CONFIG_USER_ONLY
-    { .name = "L2CTLR_EL1", .state = ARM_CP_STATE_AA64,
+    { "L2CTLR_EL1", 0, 11,0, 3,1,2, ARM_CP_STATE_AA64,
-      .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 2,
+      0, PL1_RW, NULL, 0, 0,
-      .access = PL1_RW, .readfn = a57_l2ctlr_read,
+      NULL, a57_l2ctlr_read, arm_cp_write_ignore, },
-      .writefn = arm_cp_write_ignore },
+    { "L2CTLR", 15, 9,0, 0,1,2, 0,
-    { .name = "L2CTLR",
+      0, PL1_RW, NULL, 0, 0,
-      .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 2,
+      NULL, a57_l2ctlr_read, arm_cp_write_ignore, },
-      .access = PL1_RW, .readfn = a57_l2ctlr_read,
-      .writefn = arm_cp_write_ignore },
 #endif
-    { .name = "L2ECTLR_EL1", .state = ARM_CP_STATE_AA64,
+    { "L2ECTLR_EL1", 0,11,0, 3,1,3, ARM_CP_STATE_AA64,
-      .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 3,
+      ARM_CP_CONST, PL1_RW, NULL, 0, },
-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+    { "L2ECTLR", 15,9,0, 0,1,3, 0,
-    { .name = "L2ECTLR",
+      ARM_CP_CONST, PL1_RW, NULL, 0, },
-      .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 3,
+    { "L2ACTLR", 0,15,0, 3,1,0, ARM_CP_STATE_BOTH,
-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+      ARM_CP_CONST, PL1_RW, NULL, 0 },
-    { .name = "L2ACTLR", .state = ARM_CP_STATE_BOTH,
+    { "CPUACTLR_EL1", 0,15,2, 3,1,0, ARM_CP_STATE_AA64,
-      .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 0, .opc2 = 0,
+      ARM_CP_CONST, PL1_RW, NULL, 0 },
-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+    { "CPUACTLR", 15,0,15, 0,0,0, 0,
-    { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64,
+      ARM_CP_CONST | ARM_CP_64BIT, PL1_RW, NULL, 0, },
-      .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 0,
+    { "CPUECTLR_EL1", 0,15,2, 3,1,1, ARM_CP_STATE_AA64,
-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+      ARM_CP_CONST, PL1_RW, NULL, 0, },
-    { .name = "CPUACTLR",
+    { "CPUECTLR", 15,0,15, 0,1,0, 0,
-      .cp = 15, .opc1 = 0, .crm = 15,
+      ARM_CP_CONST | ARM_CP_64BIT, PL1_RW, NULL, 0, },
-      .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
+    { "CPUMERRSR_EL1", 0,15,2, 3,1,2, ARM_CP_STATE_AA64,
-    { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64,
+      ARM_CP_CONST, PL1_RW, NULL, 0 },
-      .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 1,
+    { "CPUMERRSR", 15,0,15, 0,2,0, 0,
-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+      ARM_CP_CONST | ARM_CP_64BIT, PL1_RW, NULL, 0 },
-    { .name = "CPUECTLR",
+    { "L2MERRSR_EL1", 0,15,2, 3,1,3, ARM_CP_STATE_AA64,
-      .cp = 15, .opc1 = 1, .crm = 15,
+      ARM_CP_CONST, PL1_RW, NULL, 0 },
-      .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
+    { "L2MERRSR", 15,0,15, 0,3,0, 0,
-    { .name = "CPUMERRSR_EL1", .state = ARM_CP_STATE_AA64,
+      ARM_CP_CONST | ARM_CP_64BIT, PL1_RW, NULL, 0 },
-      .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 2,
-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-    { .name = "CPUMERRSR",
-      .cp = 15, .opc1 = 2, .crm = 15,
-      .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
-    { .name = "L2MERRSR_EL1", .state = ARM_CP_STATE_AA64,
-      .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 3,
-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-    { .name = "L2MERRSR",
-      .cp = 15, .opc1 = 3, .crm = 15,
-      .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
     REGINFO_SENTINEL
 };
 
@@ -159,11 +146,11 @@ typedef struct ARMCPUInfo {
 } ARMCPUInfo;
 
 static const ARMCPUInfo aarch64_cpus[] = {
-    { .name = "cortex-a57",         .initfn = aarch64_a57_initfn },
+    { "cortex-a57",  aarch64_a57_initfn },
 #ifdef CONFIG_USER_ONLY
-    { .name = "any",         .initfn = aarch64_any_initfn },
+    { "any",         aarch64_any_initfn },
 #endif
-    { .name = NULL }
+    { NULL }
 };
 
 static void aarch64_cpu_initfn(struct uc_struct *uc, Object *obj, void *opaque)
@@ -202,13 +189,12 @@ static void aarch64_cpu_class_init(struct uc_struct *uc, ObjectClass *oc, void *
 
 static void aarch64_cpu_register(struct uc_struct *uc, const ARMCPUInfo *info)
 {
-    TypeInfo type_info = {
+    TypeInfo type_info = { 0 };
-        .parent = TYPE_AARCH64_CPU,
+    type_info.parent = TYPE_AARCH64_CPU;
-        .instance_size = sizeof(ARMCPU),
+    type_info.instance_size = sizeof(ARMCPU);
-        .instance_init = info->initfn,
+    type_info.instance_init = info->initfn;
-        .class_size = sizeof(ARMCPUClass),
+    type_info.class_size = sizeof(ARMCPUClass);
-        .class_init = info->class_init,
+    type_info.class_init = info->class_init;
-    };
 
     type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
     type_register(uc, &type_info);
@@ -217,19 +203,18 @@ static void aarch64_cpu_register(struct uc_struct *uc, const ARMCPUInfo *info)
 
 void aarch64_cpu_register_types(void *opaque)
 {
-    static const TypeInfo aarch64_cpu_type_info = {
-        .name = TYPE_AARCH64_CPU,
-        .parent = TYPE_ARM_CPU,
-        .instance_size = sizeof(ARMCPU),
-        .instance_init = aarch64_cpu_initfn,
-        .instance_finalize = aarch64_cpu_finalizefn,
-        .abstract = true,
-        .class_size = sizeof(AArch64CPUClass),
-        .class_init = aarch64_cpu_class_init,
-    };
-
     const ARMCPUInfo *info = aarch64_cpus;
 
+    static TypeInfo aarch64_cpu_type_info = { 0 };
+    aarch64_cpu_type_info.name = TYPE_AARCH64_CPU;
+    aarch64_cpu_type_info.parent = TYPE_ARM_CPU;
+    aarch64_cpu_type_info.instance_size = sizeof(ARMCPU);
+    aarch64_cpu_type_info.instance_init = aarch64_cpu_initfn;
+    aarch64_cpu_type_info.instance_finalize = aarch64_cpu_finalizefn;
+    aarch64_cpu_type_info.abstract = true;
+    aarch64_cpu_type_info.class_size = sizeof(AArch64CPUClass);
+    aarch64_cpu_type_info.class_init = aarch64_cpu_class_init;
+
     type_register_static(opaque, &aarch64_cpu_type_info);
 
     while (info->name) {

qemu/target-arm/crypto_helper.c

@@ -28,16 +28,15 @@ void HELPER(crypto_aese)(CPUARMState *env, uint32_t rd, uint32_t rm,
     static uint8_t const * const sbox[2] = { AES_sbox, AES_isbox };
     static uint8_t const * const shift[2] = { AES_shifts, AES_ishifts };
 
-    union CRYPTO_STATE rk = { .l = {
+    union CRYPTO_STATE rk;
-        float64_val(env->vfp.regs[rm]),
+    union CRYPTO_STATE st;
-        float64_val(env->vfp.regs[rm + 1])
-    } };
-    union CRYPTO_STATE st = { .l = {
-        float64_val(env->vfp.regs[rd]),
-        float64_val(env->vfp.regs[rd + 1])
-    } };
     int i;
     
+    rk.l[0] = float64_val(env->vfp.regs[rm]);
+    rk.l[1] = float64_val(env->vfp.regs[rm + 1]);
+    st.l[0] = float64_val(env->vfp.regs[rd]);
+    st.l[1] = float64_val(env->vfp.regs[rd + 1]);
+
     assert(decrypt < 2);
 
     /* xor state vector with round key */
@@ -189,11 +188,10 @@ void HELPER(crypto_aesmc)(CPUARMState *env, uint32_t rd, uint32_t rm,
         0x92b479a7, 0x99b970a9, 0x84ae6bbb, 0x8fa362b5,
         0xbe805d9f, 0xb58d5491, 0xa89a4f83, 0xa397468d,
     } };
-    union CRYPTO_STATE st = { .l = {
+    union CRYPTO_STATE st;
-        float64_val(env->vfp.regs[rm]),
-        float64_val(env->vfp.regs[rm + 1])
-    } };
     int i;
+    st.l[0] = float64_val(env->vfp.regs[rm]);
+    st.l[1] = float64_val(env->vfp.regs[rm + 1]);
 
     assert(decrypt < 2);
 
@@ -231,18 +229,15 @@ static uint32_t maj(uint32_t x, uint32_t y, uint32_t z)
 void HELPER(crypto_sha1_3reg)(CPUARMState *env, uint32_t rd, uint32_t rn,
                               uint32_t rm, uint32_t op)
 {
-    union CRYPTO_STATE d = { .l = {
+    union CRYPTO_STATE d;
-        float64_val(env->vfp.regs[rd]),
+    union CRYPTO_STATE n;
-        float64_val(env->vfp.regs[rd + 1])
+    union CRYPTO_STATE m;
-    } };
+    d.l[0] = float64_val(env->vfp.regs[rd]);
-    union CRYPTO_STATE n = { .l = {
+    d.l[1] = float64_val(env->vfp.regs[rd + 1]);
-        float64_val(env->vfp.regs[rn]),
+    n.l[0] = float64_val(env->vfp.regs[rn]);
-        float64_val(env->vfp.regs[rn + 1])
+    n.l[1] = float64_val(env->vfp.regs[rn + 1]);
-    } };
+    m.l[0] = float64_val(env->vfp.regs[rm]);
-    union CRYPTO_STATE m = { .l = {
+    m.l[1] = float64_val(env->vfp.regs[rm + 1]);
-        float64_val(env->vfp.regs[rm]),
-        float64_val(env->vfp.regs[rm + 1])
-    } };
 
     if (op == 3) { /* sha1su0 */
         d.l[0] ^= d.l[1] ^ m.l[0];
@@ -281,10 +276,9 @@ void HELPER(crypto_sha1_3reg)(CPUARMState *env, uint32_t rd, uint32_t rn,
 
 void HELPER(crypto_sha1h)(CPUARMState *env, uint32_t rd, uint32_t rm)
 {
-    union CRYPTO_STATE m = { .l = {
+    union CRYPTO_STATE m;
-        float64_val(env->vfp.regs[rm]),
+    m.l[0] = float64_val(env->vfp.regs[rm]);
-        float64_val(env->vfp.regs[rm + 1])
+    m.l[1] = float64_val(env->vfp.regs[rm + 1]);
-    } };
 
     m.words[0] = ror32(m.words[0], 2);
     m.words[1] = m.words[2] = m.words[3] = 0;
@@ -295,14 +289,12 @@ void HELPER(crypto_sha1h)(CPUARMState *env, uint32_t rd, uint32_t rm)
 
 void HELPER(crypto_sha1su1)(CPUARMState *env, uint32_t rd, uint32_t rm)
 {
-    union CRYPTO_STATE d = { .l = {
+    union CRYPTO_STATE d;
-        float64_val(env->vfp.regs[rd]),
+    union CRYPTO_STATE m;
-        float64_val(env->vfp.regs[rd + 1])
+    d.l[0] = float64_val(env->vfp.regs[rd]);
-    } };
+    d.l[1] = float64_val(env->vfp.regs[rd + 1]);
-    union CRYPTO_STATE m = { .l = {
+    m.l[0] = float64_val(env->vfp.regs[rm]);
-        float64_val(env->vfp.regs[rm]),
+    m.l[1] = float64_val(env->vfp.regs[rm + 1]);
-        float64_val(env->vfp.regs[rm + 1])
-    } };
 
     d.words[0] = rol32(d.words[0] ^ m.words[1], 1);
     d.words[1] = rol32(d.words[1] ^ m.words[2], 1);
@@ -341,19 +333,16 @@ static uint32_t s1(uint32_t x)
 void HELPER(crypto_sha256h)(CPUARMState *env, uint32_t rd, uint32_t rn,
                             uint32_t rm)
 {
-    union CRYPTO_STATE d = { .l = {
-        float64_val(env->vfp.regs[rd]),
-        float64_val(env->vfp.regs[rd + 1])
-    } };
-    union CRYPTO_STATE n = { .l = {
-        float64_val(env->vfp.regs[rn]),
-        float64_val(env->vfp.regs[rn + 1])
-    } };
-    union CRYPTO_STATE m = { .l = {
-        float64_val(env->vfp.regs[rm]),
-        float64_val(env->vfp.regs[rm + 1])
-    } };
     int i;
+    union CRYPTO_STATE d;
+    union CRYPTO_STATE n;
+    union CRYPTO_STATE m;
+    d.l[0] = float64_val(env->vfp.regs[rd]);
+    d.l[1] = float64_val(env->vfp.regs[rd + 1]);
+    n.l[0] = float64_val(env->vfp.regs[rn]);
+    n.l[1] = float64_val(env->vfp.regs[rn + 1]);
+    m.l[0] = float64_val(env->vfp.regs[rm]);
+    m.l[1] = float64_val(env->vfp.regs[rm + 1]);
 
     for (i = 0; i < 4; i++) {
         uint32_t t = cho(n.words[0], n.words[1], n.words[2]) + n.words[3]
@@ -379,20 +368,18 @@ void HELPER(crypto_sha256h)(CPUARMState *env, uint32_t rd, uint32_t rn,
 void HELPER(crypto_sha256h2)(CPUARMState *env, uint32_t rd, uint32_t rn,
                              uint32_t rm)
 {
-    union CRYPTO_STATE d = { .l = {
+    union CRYPTO_STATE d;
-        float64_val(env->vfp.regs[rd]),
+    union CRYPTO_STATE n;
-        float64_val(env->vfp.regs[rd + 1])
+    union CRYPTO_STATE m;
-    } };
-    union CRYPTO_STATE n = { .l = {
-        float64_val(env->vfp.regs[rn]),
-        float64_val(env->vfp.regs[rn + 1])
-    } };
-    union CRYPTO_STATE m = { .l = {
-        float64_val(env->vfp.regs[rm]),
-        float64_val(env->vfp.regs[rm + 1])
-    } };
     int i;
     
+    d.l[0] = float64_val(env->vfp.regs[rd]);
+    d.l[1] = float64_val(env->vfp.regs[rd + 1]);
+    n.l[0] = float64_val(env->vfp.regs[rn]);
+    n.l[1] = float64_val(env->vfp.regs[rn + 1]);
+    m.l[0] = float64_val(env->vfp.regs[rm]);
+    m.l[1] = float64_val(env->vfp.regs[rm + 1]);
+
     for (i = 0; i < 4; i++) {
         uint32_t t = cho(d.words[0], d.words[1], d.words[2]) + d.words[3]
                      + S1(d.words[0]) + m.words[i];
@@ -409,14 +396,12 @@ void HELPER(crypto_sha256h2)(CPUARMState *env, uint32_t rd, uint32_t rn,
 
 void HELPER(crypto_sha256su0)(CPUARMState *env, uint32_t rd, uint32_t rm)
 {
-    union CRYPTO_STATE d = { .l = {
+    union CRYPTO_STATE d;
-        float64_val(env->vfp.regs[rd]),
+    union CRYPTO_STATE m;
-        float64_val(env->vfp.regs[rd + 1])
+    d.l[0] = float64_val(env->vfp.regs[rd]);
-    } };
+    d.l[1] = float64_val(env->vfp.regs[rd + 1]);
-    union CRYPTO_STATE m = { .l = {
+    m.l[0] = float64_val(env->vfp.regs[rm]);
-        float64_val(env->vfp.regs[rm]),
+    m.l[1] = float64_val(env->vfp.regs[rm + 1]);
-        float64_val(env->vfp.regs[rm + 1])
-    } };
 
     d.words[0] += s0(d.words[1]);
     d.words[1] += s0(d.words[2]);
@@ -430,18 +415,15 @@ void HELPER(crypto_sha256su0)(CPUARMState *env, uint32_t rd, uint32_t rm)
 void HELPER(crypto_sha256su1)(CPUARMState *env, uint32_t rd, uint32_t rn,
                               uint32_t rm)
 {
-    union CRYPTO_STATE d = { .l = {
+    union CRYPTO_STATE d;
-        float64_val(env->vfp.regs[rd]),
+    union CRYPTO_STATE n;
-        float64_val(env->vfp.regs[rd + 1])
+    union CRYPTO_STATE m;
-    } };
+    d.l[0] = float64_val(env->vfp.regs[rd]);
-    union CRYPTO_STATE n = { .l = {
+    d.l[1] = float64_val(env->vfp.regs[rd + 1]);
-        float64_val(env->vfp.regs[rn]),
+    n.l[0] = float64_val(env->vfp.regs[rn]);
-        float64_val(env->vfp.regs[rn + 1])
+    n.l[1] = float64_val(env->vfp.regs[rn + 1]);
-    } };
+    m.l[0] = float64_val(env->vfp.regs[rm]);
-    union CRYPTO_STATE m = { .l = {
+    m.l[1] = float64_val(env->vfp.regs[rm + 1]);
-        float64_val(env->vfp.regs[rm]),
-        float64_val(env->vfp.regs[rm + 1])
-    } };
 
     d.words[0] += s1(m.words[2]) + n.words[1];
     d.words[1] += s1(m.words[3]) + n.words[2];

qemu/target-arm/internals.h

@@ -43,21 +43,22 @@ static inline bool excp_is_internal(int excp)
  * precisely correspond to architectural exceptions.
  */
 static const char * const excnames[] = {
-    [EXCP_UDEF] = "Undefined Instruction",
+    NULL,
-    [EXCP_SWI] = "SVC",
+    "Undefined Instruction",
-    [EXCP_PREFETCH_ABORT] = "Prefetch Abort",
+    "SVC",
-    [EXCP_DATA_ABORT] = "Data Abort",
+    "Prefetch Abort",
-    [EXCP_IRQ] = "IRQ",
+    "Data Abort",
-    [EXCP_FIQ] = "FIQ",
+    "IRQ",
-    [EXCP_BKPT] = "Breakpoint",
+    "FIQ",
-    [EXCP_EXCEPTION_EXIT] = "QEMU v7M exception exit",
+    "Breakpoint",
-    [EXCP_KERNEL_TRAP] = "QEMU intercept of kernel commpage",
+    "QEMU v7M exception exit",
-    [EXCP_STREX] = "QEMU intercept of STREX",
+     "QEMU intercept of kernel commpage",
-    [EXCP_HVC] = "Hypervisor Call",
+    "QEMU intercept of STREX",
-    [EXCP_HYP_TRAP] = "Hypervisor Trap",
+    "Hypervisor Call",
-    [EXCP_SMC] = "Secure Monitor Call",
+    "Hypervisor Trap",
-    [EXCP_VIRQ] = "Virtual IRQ",
+    "Secure Monitor Call",
-    [EXCP_VFIQ] = "Virtual FIQ",
+    "Virtual IRQ",
+    "Virtual FIQ",
 };
 
 static inline void arm_log_exception(int idx)
@@ -86,9 +87,10 @@ static inline void arm_log_exception(int idx)
 static inline unsigned int aarch64_banked_spsr_index(unsigned int el)
 {
     static const unsigned int map[4] = {
-        [1] = 0, /* EL1.  */
+        0,
-        [2] = 6, /* EL2.  */
+        0, /* EL1.  */
-        [3] = 7, /* EL3.  */
+        6, /* EL2.  */
+        7, /* EL3.  */
     };
     assert(el >= 1 && el <= 3);
     return map[el];

qemu/target-arm/neon_helper.c

@@ -704,7 +704,7 @@ uint32_t HELPER(neon_rshl_s32)(uint32_t valop, uint32_t shiftop)
     if ((shift >= 32) || (shift <= -32)) {
         dest = 0;
     } else if (shift < 0) {
-        int64_t big_dest = ((int64_t)val + (1 << (-1 - shift)));
+        int64_t big_dest = ((int64_t)val + (1ULL << (-1 - shift)));
         dest = big_dest >> -shift;
     } else {
         dest = val << shift;
@@ -765,7 +765,7 @@ uint32_t HELPER(neon_rshl_u32)(uint32_t val, uint32_t shiftop)
     } else if (shift == -32) {
         dest = val >> 31;
     } else if (shift < 0) {
-        uint64_t big_dest = ((uint64_t)val + (1 << (-1 - shift)));
+        uint64_t big_dest = ((uint64_t)val + (1ULL << (-1 - shift)));
         dest = big_dest >> -shift;
     } else {
         dest = val << shift;
@@ -998,7 +998,7 @@ uint32_t HELPER(neon_qrshl_u32)(CPUARMState *env, uint32_t val, uint32_t shiftop
     } else if (shift == -32) {
         dest = val >> 31;
     } else if (shift < 0) {
-        uint64_t big_dest = ((uint64_t)val + (1 << (-1 - shift)));
+        uint64_t big_dest = ((uint64_t)val + (1ULL << (-1 - shift)));
         dest = big_dest >> -shift;
     } else {
         dest = val << shift;
@@ -1094,7 +1094,7 @@ uint32_t HELPER(neon_qrshl_s32)(CPUARMState *env, uint32_t valop, uint32_t shift
     } else if (shift <= -32) {
         dest = 0;
     } else if (shift < 0) {
-        int64_t big_dest = ((int64_t)val + (1 << (-1 - shift)));
+        int64_t big_dest = ((int64_t)val + (1ULL << (-1 - shift)));
         dest = big_dest >> -shift;
     } else {
         dest = val << shift;
@@ -1824,20 +1824,20 @@ uint64_t HELPER(neon_negl_u16)(uint64_t x)
 {
     uint16_t tmp;
     uint64_t result;
-    result = (uint16_t)-x;
+    result = (uint16_t)(0-x);
-    tmp = -(x >> 16);
+    tmp = 0-(x >> 16);
     result |= (uint64_t)tmp << 16;
-    tmp = -(x >> 32);
+    tmp = 0-(x >> 32);
     result |= (uint64_t)tmp << 32;
-    tmp = -(x >> 48);
+    tmp = 0-(x >> 48);
     result |= (uint64_t)tmp << 48;
     return result;
 }
 
 uint64_t HELPER(neon_negl_u32)(uint64_t x)
 {
-    uint32_t low = -x;
+    uint32_t low = 0-x;
-    uint32_t high = -(x >> 32);
+    uint32_t high = 0-(x >> 32);
     return low | ((uint64_t)high << 32);
 }
 
@@ -1925,7 +1925,7 @@ uint32_t HELPER(neon_qabs_s32)(CPUARMState *env, uint32_t x)
         SET_QC();
         x = ~SIGNBIT;
     } else if ((int32_t)x < 0) {
-        x = -x;
+        x = 0-x;
     }
     return x;
 }
@@ -1936,7 +1936,7 @@ uint32_t HELPER(neon_qneg_s32)(CPUARMState *env, uint32_t x)
         SET_QC();
         x = ~SIGNBIT;
     } else {
-        x = -x;
+        x = 0-x;
     }
     return x;
 }
@@ -1947,7 +1947,7 @@ uint64_t HELPER(neon_qabs_s64)(CPUARMState *env, uint64_t x)
         SET_QC();
         x = ~SIGNBIT64;
     } else if ((int64_t)x < 0) {
-        x = -x;
+        x = 0-x;
     }
     return x;
 }
@@ -1958,7 +1958,7 @@ uint64_t HELPER(neon_qneg_s64)(CPUARMState *env, uint64_t x)
         SET_QC();
         x = ~SIGNBIT64;
     } else {
-        x = -x;
+        x = 0-x;
     }
     return x;
 }

qemu/target-arm/translate-a64.c

@@ -1679,7 +1679,7 @@ static void gen_load_exclusive(DisasContext *s, int rt, int rt2,
         TCGv_i64 hitmp = tcg_temp_new_i64(tcg_ctx);
 
         g_assert(size >= 2);
-        tcg_gen_addi_i64(tcg_ctx, addr2, addr, 1 << size);
+        tcg_gen_addi_i64(tcg_ctx, addr2, addr, 1ULL << size);
         tcg_gen_qemu_ld_i64(s->uc, hitmp, addr2, get_mem_index(s), memop);
         tcg_temp_free_i64(tcg_ctx, addr2);
         tcg_gen_mov_i64(tcg_ctx, tcg_ctx->cpu_exclusive_high, hitmp);
@@ -1740,7 +1740,7 @@ static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,
         TCGv_i64 addrhi = tcg_temp_new_i64(tcg_ctx);
         TCGv_i64 tmphi = tcg_temp_new_i64(tcg_ctx);
 
-        tcg_gen_addi_i64(tcg_ctx, addrhi, addr, 1 << size);
+        tcg_gen_addi_i64(tcg_ctx, addrhi, addr, 1ULL << size);
         tcg_gen_qemu_ld_i64(s->uc, tmphi, addrhi, get_mem_index(s), MO_TE + size);
         tcg_gen_brcond_i64(tcg_ctx, TCG_COND_NE, tmphi, tcg_ctx->cpu_exclusive_high, fail_label);
 
@@ -1753,7 +1753,7 @@ static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,
     if (is_pair) {
         TCGv_i64 addrhi = tcg_temp_new_i64(tcg_ctx);
 
-        tcg_gen_addi_i64(tcg_ctx, addrhi, addr, 1 << size);
+        tcg_gen_addi_i64(tcg_ctx, addrhi, addr, 1ULL << size);
         tcg_gen_qemu_st_i64(s->uc, cpu_reg(s, rt2), addrhi,
                             get_mem_index(s), MO_TE + size);
         tcg_temp_free_i64(tcg_ctx, addrhi);
@@ -1832,7 +1832,7 @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn)
         }
         if (is_pair) {
             TCGv_i64 tcg_rt2 = cpu_reg(s, rt);
-            tcg_gen_addi_i64(tcg_ctx, tcg_addr, tcg_addr, 1 << size);
+            tcg_gen_addi_i64(tcg_ctx, tcg_addr, tcg_addr, 1ULL << size);
             if (is_store) {
                 do_gpr_st(s, tcg_rt2, tcg_addr, size);
             } else {
@@ -2015,7 +2015,7 @@ static void disas_ldst_pair(DisasContext *s, uint32_t insn)
             do_gpr_st(s, tcg_rt, tcg_addr, size);
         }
     }
-    tcg_gen_addi_i64(tcg_ctx, tcg_addr, tcg_addr, 1 << size);
+    tcg_gen_addi_i64(tcg_ctx, tcg_addr, tcg_addr, 1ULL << size);
     if (is_vector) {
         if (is_load) {
             do_fp_ld(s, rt2, tcg_addr, size);
@@ -2033,9 +2033,9 @@ static void disas_ldst_pair(DisasContext *s, uint32_t insn)
 
     if (wback) {
         if (postindex) {
-            tcg_gen_addi_i64(tcg_ctx, tcg_addr, tcg_addr, offset - (1 << size));
+            tcg_gen_addi_i64(tcg_ctx, tcg_addr, tcg_addr, offset - (1ULL << size));
         } else {
-            tcg_gen_subi_i64(tcg_ctx, tcg_addr, tcg_addr, 1 << size);
+            tcg_gen_subi_i64(tcg_ctx, tcg_addr, tcg_addr, 1ULL << size);
         }
         tcg_gen_mov_i64(tcg_ctx, cpu_reg_sp(s, rn), tcg_addr);
     }
@@ -4449,9 +4449,9 @@ static void disas_fp_1src(DisasContext *s, uint32_t insn)
         handle_fp_fcvt(s, opcode, rd, rn, dtype, type);
         break;
     }
-    case 0x0 ... 0x3:
+    case 0x0: case 0x1: case 0x2: case 0x3:
-    case 0x8 ... 0xc:
+    case 0x8: case 0x9: case 0xa: case 0xb: case 0xc:
-    case 0xe ... 0xf:
+    case 0xe: case 0xf:
         /* 32-to-32 and 64-to-64 ops */
         switch (type) {
         case 0:
@@ -5920,7 +5920,7 @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
             int i;
             imm = 0;
             for (i = 0; i < 8; i++) {
-                if ((abcdefgh) & (1 << i)) {
+                if ((abcdefgh) & (1ULL << i)) {
                     imm |= 0xffULL << (i * 8);
                 }
             }
@@ -7940,8 +7940,8 @@ static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn)
         }
         handle_2misc_narrow(s, true, opcode, u, false, size, rn, rd);
         return;
-    case 0xc ... 0xf:
+    case 0x0c: case 0x0d: case 0x0e: case 0x0f:
-    case 0x16 ... 0x1d:
+    case 0x16: case 0x17: case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d:
     case 0x1f:
         /* Floating point: U, size[1] and opcode indicate operation;
          * size[0] indicates single or double precision.
@@ -9523,7 +9523,10 @@ static void disas_simd_three_reg_same(DisasContext *s, uint32_t insn)
         handle_simd_3same_pair(s, is_q, u, opcode, size, rn, rm, rd);
         break;
     }
-    case 0x18 ... 0x31:
+    case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f:
+    case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
+    case 0x28: case 0x29: case 0x2a: case 0x2b: case 0x2c: case 0x2d: case 0x2e: case 0x2f:
+    case 0x30: case 0x31:
         /* floating point ops, sz[1] and U are part of opcode */
         disas_simd_3same_float(s, insn);
         break;
@@ -9866,8 +9869,8 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
             return;
         }
         break;
-    case 0xc ... 0xf:
+    case 0x0c: case 0x0d: case 0x0e: case 0x0f:
-    case 0x16 ... 0x1d:
+    case 0x16: case 0x17: case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d:
     case 0x1f:
     {
         /* Floating point: U, size[1] and opcode indicate operation;

qemu/target-arm/translate.c

@@ -1568,7 +1568,7 @@ static inline int gen_iwmmxt_address(DisasContext *s, uint32_t insn,
         if (insn & (1 << 23))
             tcg_gen_addi_i32(tcg_ctx, tmp, tmp, offset);
         else
-            tcg_gen_addi_i32(tcg_ctx, tmp, tmp, -offset);
+            tcg_gen_addi_i32(tcg_ctx, tmp, tmp, 0-offset);
         tcg_gen_mov_i32(tcg_ctx, dest, tmp);
         if (insn & (1 << 21))
             store_reg(s, rd, tmp);
@@ -1580,7 +1580,7 @@ static inline int gen_iwmmxt_address(DisasContext *s, uint32_t insn,
         if (insn & (1 << 23))
             tcg_gen_addi_i32(tcg_ctx, tmp, tmp, offset);
         else
-            tcg_gen_addi_i32(tcg_ctx, tmp, tmp, -offset);
+            tcg_gen_addi_i32(tcg_ctx, tmp, tmp, 0-offset);
         store_reg(s, rd, tmp);
     } else if (!(insn & (1 << 23)))
         return 1;
@@ -2688,9 +2688,20 @@ static int disas_dsp_insn(DisasContext *s, uint32_t insn)
     return 1;
 }
 
-#define VFP_REG_SHR(x, n) (((n) > 0) ? (x) >> (n) : (x) << -(n))
+// this causes "warning C4293: shift count negative or too big, undefined behavior"
-#define VFP_SREG(insn, bigbit, smallbit) \
+// on msvc, so is replaced with separate versions for the shift to perform.
-  ((VFP_REG_SHR(insn, bigbit - 1) & 0x1e) | (((insn) >> (smallbit)) & 1))
+//#define VFP_REG_SHR(x, n) (((n) > 0) ? (x) >> (n) : (x) << -(n))
+//#define VFP_SREG(insn, bigbit, smallbit) \
+//  ((VFP_REG_SHR(insn, bigbit - 1) & 0x1e) | (((insn) >> (smallbit)) & 1))
+
+#define VFP_REG_SHR_NEG(insn, n) ((insn) << -(n))
+#define VFP_SREG_NEG(insn, bigbit, smallbit) \
+  ((VFP_REG_SHR_NEG(insn, bigbit - 1) & 0x1e) | (((insn) >> (smallbit)) & 1))
+
+#define VFP_REG_SHR_POS(x, n) ((insn) >> (n))
+#define VFP_SREG_POS(insn, bigbit, smallbit) \
+  ((VFP_REG_SHR_POS(insn, bigbit - 1) & 0x1e) | (((insn) >> (smallbit)) & 1))
+
 #define VFP_DREG(reg, insn, bigbit, smallbit) do { \
     if (arm_dc_feature(s, ARM_FEATURE_VFP3)) { \
         reg = (((insn) >> (bigbit)) & 0x0f) \
@@ -2701,11 +2712,11 @@ static int disas_dsp_insn(DisasContext *s, uint32_t insn)
         reg = ((insn) >> (bigbit)) & 0x0f; \
     }} while (0)
 
-#define VFP_SREG_D(insn) VFP_SREG(insn, 12, 22)
+#define VFP_SREG_D(insn) VFP_SREG_POS(insn, 12, 22)
 #define VFP_DREG_D(reg, insn) VFP_DREG(reg, insn, 12, 22)
-#define VFP_SREG_N(insn) VFP_SREG(insn, 16,  7)
+#define VFP_SREG_N(insn) VFP_SREG_POS(insn, 16,  7)
 #define VFP_DREG_N(reg, insn) VFP_DREG(reg, insn, 16,  7)
-#define VFP_SREG_M(insn) VFP_SREG(insn,  0,  5)
+#define VFP_SREG_M(insn) VFP_SREG_NEG(insn,  0,  5)
 #define VFP_DREG_M(reg, insn) VFP_DREG(reg, insn,  0,  5)
 
 /* Move between integer and VFP cores.  */
@@ -3913,7 +3924,7 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)
                 /* Single load/store */
                 offset = (insn & 0xff) << 2;
                 if ((insn & (1 << 23)) == 0)
-                    offset = -offset;
+                    offset = 0-offset;
                 if (s->thumb && rn == 15) {
                     /* This is actually UNPREDICTABLE */
                     addr = tcg_temp_new_i32(tcg_ctx);
@@ -3961,7 +3972,7 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)
                     addr = load_reg(s, rn);
                 }
                 if (insn & (1 << 24)) /* pre-decrement */
-                    tcg_gen_addi_i32(tcg_ctx, addr, addr, -((insn & 0xff) << 2));
+                    tcg_gen_addi_i32(tcg_ctx, addr, addr, 0-((insn & 0xff) << 2));
 
                 if (dp)
                     offset = 8;
@@ -3982,7 +3993,7 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)
                 if (w) {
                     /* writeback */
                     if (insn & (1 << 24))
-                        offset = -offset * n;
+                        offset = (0-offset) * n;
                     else if (dp && (insn & 1))
                         offset = 4;
                     else
@@ -4976,38 +4987,38 @@ static void gen_neon_narrow_op(DisasContext *s, int op, int u, int size,
 #define NEON_3R_FLOAT_MISC 31 /* float VRECPS, VRSQRTS, VMAXNM/MINNM */
 
 static const uint8_t neon_3r_sizes[] = {
-    [NEON_3R_VHADD] = 0x7,
+    /*NEON_3R_VHADD*/ 0x7,
-    [NEON_3R_VQADD] = 0xf,
+    /*NEON_3R_VQADD*/ 0xf,
-    [NEON_3R_VRHADD] = 0x7,
+    /*NEON_3R_VRHADD*/ 0x7,
-    [NEON_3R_LOGIC] = 0xf, /* size field encodes op type */
+    /*NEON_3R_LOGIC*/ 0xf, /* size field encodes op type */
-    [NEON_3R_VHSUB] = 0x7,
+    /*NEON_3R_VHSUB*/ 0x7,
-    [NEON_3R_VQSUB] = 0xf,
+    /*NEON_3R_VQSUB*/ 0xf,
-    [NEON_3R_VCGT] = 0x7,
+    /*NEON_3R_VCGT*/ 0x7,
-    [NEON_3R_VCGE] = 0x7,
+    /*NEON_3R_VCGE*/ 0x7,
-    [NEON_3R_VSHL] = 0xf,
+    /*NEON_3R_VSHL*/ 0xf,
-    [NEON_3R_VQSHL] = 0xf,
+    /*NEON_3R_VQSHL*/ 0xf,
-    [NEON_3R_VRSHL] = 0xf,
+    /*NEON_3R_VRSHL*/ 0xf,
-    [NEON_3R_VQRSHL] = 0xf,
+    /*NEON_3R_VQRSHL*/ 0xf,
-    [NEON_3R_VMAX] = 0x7,
+    /*NEON_3R_VMAX*/ 0x7,
-    [NEON_3R_VMIN] = 0x7,
+    /*NEON_3R_VMIN*/ 0x7,
-    [NEON_3R_VABD] = 0x7,
+    /*NEON_3R_VABD*/ 0x7,
-    [NEON_3R_VABA] = 0x7,
+    /*NEON_3R_VABA*/ 0x7,
-    [NEON_3R_VADD_VSUB] = 0xf,
+    /*NEON_3R_VADD_VSUB*/ 0xf,
-    [NEON_3R_VTST_VCEQ] = 0x7,
+    /*NEON_3R_VTST_VCEQ*/ 0x7,
-    [NEON_3R_VML] = 0x7,
+    /*NEON_3R_VML*/ 0x7,
-    [NEON_3R_VMUL] = 0x7,
+    /*NEON_3R_VMUL*/ 0x7,
-    [NEON_3R_VPMAX] = 0x7,
+    /*NEON_3R_VPMAX*/ 0x7,
-    [NEON_3R_VPMIN] = 0x7,
+    /*NEON_3R_VPMIN*/ 0x7,
-    [NEON_3R_VQDMULH_VQRDMULH] = 0x6,
+    /*NEON_3R_VQDMULH_VQRDMULH*/ 0x6,
-    [NEON_3R_VPADD] = 0x7,
+    /*NEON_3R_VPADD*/ 0x7,
-    [NEON_3R_SHA] = 0xf, /* size field encodes op type */
+    /*NEON_3R_SHA*/ 0xf, /* size field encodes op type */
-    [NEON_3R_VFM] = 0x5, /* size bit 1 encodes op */
+    /*NEON_3R_VFM*/ 0x5, /* size bit 1 encodes op */
-    [NEON_3R_FLOAT_ARITH] = 0x5, /* size bit 1 encodes op */
+    /*NEON_3R_FLOAT_ARITH*/ 0x5, /* size bit 1 encodes op */
-    [NEON_3R_FLOAT_MULTIPLY] = 0x5, /* size bit 1 encodes op */
+    /*NEON_3R_FLOAT_MULTIPLY*/ 0x5, /* size bit 1 encodes op */
-    [NEON_3R_FLOAT_CMP] = 0x5, /* size bit 1 encodes op */
+    /*NEON_3R_FLOAT_CMP*/ 0x5, /* size bit 1 encodes op */
-    [NEON_3R_FLOAT_ACMP] = 0x5, /* size bit 1 encodes op */
+    /*NEON_3R_FLOAT_ACMP*/ 0x5, /* size bit 1 encodes op */
-    [NEON_3R_FLOAT_MINMAX] = 0x5, /* size bit 1 encodes op */
+    /*NEON_3R_FLOAT_MINMAX*/ 0x5, /* size bit 1 encodes op */
-    [NEON_3R_FLOAT_MISC] = 0x5, /* size bit 1 encodes op */
+    /*NEON_3R_FLOAT_MISC*/ 0x5, /* size bit 1 encodes op */
 };
 
 /* Symbolic constants for op fields for Neon 2-register miscellaneous.
@@ -5092,68 +5103,70 @@ static int neon_2rm_is_float_op(int op)
  * op values will have no bits set they always UNDEF.
  */
 static const uint8_t neon_2rm_sizes[] = {
-    [NEON_2RM_VREV64] = 0x7,
+    /*NEON_2RM_VREV64*/ 0x7,
-    [NEON_2RM_VREV32] = 0x3,
+    /*NEON_2RM_VREV32*/ 0x3,
-    [NEON_2RM_VREV16] = 0x1,
+    /*NEON_2RM_VREV16*/ 0x1,
-    [NEON_2RM_VPADDL] = 0x7,
+    0,
-    [NEON_2RM_VPADDL_U] = 0x7,
+    /*NEON_2RM_VPADDL*/ 0x7,
-    [NEON_2RM_AESE] = 0x1,
+    /*NEON_2RM_VPADDL_U*/ 0x7,
-    [NEON_2RM_AESMC] = 0x1,
+    /*NEON_2RM_AESE*/ 0x1,
-    [NEON_2RM_VCLS] = 0x7,
+    /*NEON_2RM_AESMC*/ 0x1,
-    [NEON_2RM_VCLZ] = 0x7,
+    /*NEON_2RM_VCLS*/ 0x7,
-    [NEON_2RM_VCNT] = 0x1,
+    /*NEON_2RM_VCLZ*/ 0x7,
-    [NEON_2RM_VMVN] = 0x1,
+    /*NEON_2RM_VCNT*/ 0x1,
-    [NEON_2RM_VPADAL] = 0x7,
+    /*NEON_2RM_VMVN*/ 0x1,
-    [NEON_2RM_VPADAL_U] = 0x7,
+    /*NEON_2RM_VPADAL*/ 0x7,
-    [NEON_2RM_VQABS] = 0x7,
+    /*NEON_2RM_VPADAL_U*/ 0x7,
-    [NEON_2RM_VQNEG] = 0x7,
+    /*NEON_2RM_VQABS*/ 0x7,
-    [NEON_2RM_VCGT0] = 0x7,
+    /*NEON_2RM_VQNEG*/ 0x7,
-    [NEON_2RM_VCGE0] = 0x7,
+    /*NEON_2RM_VCGT0*/ 0x7,
-    [NEON_2RM_VCEQ0] = 0x7,
+    /*NEON_2RM_VCGE0*/ 0x7,
-    [NEON_2RM_VCLE0] = 0x7,
+    /*NEON_2RM_VCEQ0*/ 0x7,
-    [NEON_2RM_VCLT0] = 0x7,
+    /*NEON_2RM_VCLE0*/ 0x7,
-    [NEON_2RM_SHA1H] = 0x4,
+    /*NEON_2RM_VCLT0*/ 0x7,
-    [NEON_2RM_VABS] = 0x7,
+    /*NEON_2RM_SHA1H*/ 0x4,
-    [NEON_2RM_VNEG] = 0x7,
+    /*NEON_2RM_VABS*/ 0x7,
-    [NEON_2RM_VCGT0_F] = 0x4,
+    /*NEON_2RM_VNEG*/ 0x7,
-    [NEON_2RM_VCGE0_F] = 0x4,
+    /*NEON_2RM_VCGT0_F*/ 0x4,
-    [NEON_2RM_VCEQ0_F] = 0x4,
+    /*NEON_2RM_VCGE0_F*/ 0x4,
-    [NEON_2RM_VCLE0_F] = 0x4,
+    /*NEON_2RM_VCEQ0_F*/ 0x4,
-    [NEON_2RM_VCLT0_F] = 0x4,
+    /*NEON_2RM_VCLE0_F*/ 0x4,
-    [NEON_2RM_VABS_F] = 0x4,
+    /*NEON_2RM_VCLT0_F*/ 0x4,
-    [NEON_2RM_VNEG_F] = 0x4,
+    0,
-    [NEON_2RM_VSWP] = 0x1,
+    /*NEON_2RM_VABS_F*/ 0x4,
-    [NEON_2RM_VTRN] = 0x7,
+    /*NEON_2RM_VNEG_F*/ 0x4,
-    [NEON_2RM_VUZP] = 0x7,
+    /*NEON_2RM_VSWP*/ 0x1,
-    [NEON_2RM_VZIP] = 0x7,
+    /*NEON_2RM_VTRN*/ 0x7,
-    [NEON_2RM_VMOVN] = 0x7,
+    /*NEON_2RM_VUZP*/ 0x7,
-    [NEON_2RM_VQMOVN] = 0x7,
+    /*NEON_2RM_VZIP*/ 0x7,
-    [NEON_2RM_VSHLL] = 0x7,
+    /*NEON_2RM_VMOVN*/ 0x7,
-    [NEON_2RM_SHA1SU1] = 0x4,
+    /*NEON_2RM_VQMOVN*/ 0x7,
-    [NEON_2RM_VRINTN] = 0x4,
+    /*NEON_2RM_VSHLL*/ 0x7,
-    [NEON_2RM_VRINTX] = 0x4,
+    /*NEON_2RM_SHA1SU1*/ 0x4,
-    [NEON_2RM_VRINTA] = 0x4,
+    /*NEON_2RM_VRINTN*/ 0x4,
-    [NEON_2RM_VRINTZ] = 0x4,
+    /*NEON_2RM_VRINTX*/ 0x4,
-    [NEON_2RM_VCVT_F16_F32] = 0x2,
+    /*NEON_2RM_VRINTA*/ 0x4,
-    [NEON_2RM_VRINTM] = 0x4,
+    /*NEON_2RM_VRINTZ*/ 0x4,
-    [NEON_2RM_VCVT_F32_F16] = 0x2,
+    /*NEON_2RM_VCVT_F16_F32*/ 0x2,
-    [NEON_2RM_VRINTP] = 0x4,
+    /*NEON_2RM_VRINTM*/ 0x4,
-    [NEON_2RM_VCVTAU] = 0x4,
+    /*NEON_2RM_VCVT_F32_F16*/ 0x2,
-    [NEON_2RM_VCVTAS] = 0x4,
+    /*NEON_2RM_VRINTP*/ 0x4,
-    [NEON_2RM_VCVTNU] = 0x4,
+    /*NEON_2RM_VCVTAU*/ 0x4,
-    [NEON_2RM_VCVTNS] = 0x4,
+    /*NEON_2RM_VCVTAS*/ 0x4,
-    [NEON_2RM_VCVTPU] = 0x4,
+    /*NEON_2RM_VCVTNU*/ 0x4,
-    [NEON_2RM_VCVTPS] = 0x4,
+    /*NEON_2RM_VCVTNS*/ 0x4,
-    [NEON_2RM_VCVTMU] = 0x4,
+    /*NEON_2RM_VCVTPU*/ 0x4,
-    [NEON_2RM_VCVTMS] = 0x4,
+    /*NEON_2RM_VCVTPS*/ 0x4,
-    [NEON_2RM_VRECPE] = 0x4,
+    /*NEON_2RM_VCVTMU*/ 0x4,
-    [NEON_2RM_VRSQRTE] = 0x4,
+    /*NEON_2RM_VCVTMS*/ 0x4,
-    [NEON_2RM_VRECPE_F] = 0x4,
+    /*NEON_2RM_VRECPE*/ 0x4,
-    [NEON_2RM_VRSQRTE_F] = 0x4,
+    /*NEON_2RM_VRSQRTE*/ 0x4,
-    [NEON_2RM_VCVT_FS] = 0x4,
+    /*NEON_2RM_VRECPE_F*/ 0x4,
-    [NEON_2RM_VCVT_FU] = 0x4,
+    /*NEON_2RM_VRSQRTE_F*/ 0x4,
-    [NEON_2RM_VCVT_SF] = 0x4,
+    /*NEON_2RM_VCVT_FS*/ 0x4,
-    [NEON_2RM_VCVT_UF] = 0x4,
+    /*NEON_2RM_VCVT_FU*/ 0x4,
+    /*NEON_2RM_VCVT_SF*/ 0x4,
+    /*NEON_2RM_VCVT_UF*/ 0x4,
 };
 
 /* Translate a NEON data processing instruction.  Return nonzero if the
@@ -5803,8 +5816,8 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
                             tcg_gen_add_i64(tcg_ctx, tcg_ctx->cpu_V0, tcg_ctx->cpu_V0, tcg_ctx->cpu_V1);
                         } else if (op == 4 || (op == 5 && u)) {
                             /* Insert */
-                            neon_load_reg64(tcg_ctx, tcg_ctx->cpu_V1, rd + pass);
                             uint64_t mask;
+                            neon_load_reg64(tcg_ctx, tcg_ctx->cpu_V1, rd + pass);
                             if (shift < -63 || shift > 63) {
                                 mask = 0;
                             } else {
@@ -9283,7 +9296,7 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
                 }
                 offset = (insn & 0xff) * 4;
                 if ((insn & (1 << 23)) == 0)
-                    offset = -offset;
+                    offset = 0-offset;
                 if (insn & (1 << 24)) {
                     tcg_gen_addi_i32(tcg_ctx, addr, addr, offset);
                     offset = 0;
@@ -9465,7 +9478,7 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
                         offset += 4;
                 }
                 if (insn & (1 << 24)) {
-                    tcg_gen_addi_i32(tcg_ctx, addr, addr, -offset);
+                    tcg_gen_addi_i32(tcg_ctx, addr, addr, 0-offset);
                 }
 
                 TCGV_UNUSED_I32(loaded_var);
@@ -9498,7 +9511,7 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
                 if (insn & (1 << 21)) {
                     /* Base register writeback.  */
                     if (insn & (1 << 24)) {
-                        tcg_gen_addi_i32(tcg_ctx, addr, addr, -offset);
+                        tcg_gen_addi_i32(tcg_ctx, addr, addr, 0-offset);
                     }
                     /* Fault if writeback register is in register list.  */
                     if (insn & (1 << rn))
@@ -10287,21 +10300,21 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
                     tcg_temp_free_i32(tcg_ctx, tmp);
                     break;
                 case 0xc: /* Negative offset.  */
-                    tcg_gen_addi_i32(tcg_ctx, addr, addr, -imm);
+                    tcg_gen_addi_i32(tcg_ctx, addr, addr, 0-imm);
                     break;
                 case 0xe: /* User privilege.  */
                     tcg_gen_addi_i32(tcg_ctx, addr, addr, imm);
                     memidx = MMU_USER_IDX;
                     break;
                 case 0x9: /* Post-decrement.  */
-                    imm = -imm;
+                    imm = 0-imm;
                     /* Fall through.  */
                 case 0xb: /* Post-increment.  */
                     postinc = 1;
                     writeback = 1;
                     break;
                 case 0xd: /* Pre-decrement.  */
-                    imm = -imm;
+                    imm = 0-imm;
                     /* Fall through.  */
                 case 0xf: /* Pre-increment.  */
                     tcg_gen_addi_i32(tcg_ctx, addr, addr, imm);

qemu/target-arm/unicorn_aarch64.c

@@ -21,11 +21,13 @@ void arm64_release(void* ctx);
 
 void arm64_release(void* ctx)
 {
+    struct uc_struct* uc;
+    ARMCPU* cpu;
     TCGContext *s = (TCGContext *) ctx;
 
     g_free(s->tb_ctx.tbs);
-    struct uc_struct* uc = s->uc;
+    uc = s->uc;
-    ARMCPU* cpu = (ARMCPU*) uc->cpu;
+    cpu = (ARMCPU*) uc->cpu;
     g_free(cpu->cpreg_indexes);
     g_free(cpu->cpreg_values);
     g_free(cpu->cpreg_vmstate_indexes);

qemu/target-arm/unicorn_arm.c

@@ -22,11 +22,13 @@ void arm_release(void* ctx);
 
 void arm_release(void* ctx)
 {
+    ARMCPU* cpu;
+    struct uc_struct* uc;
     TCGContext *s = (TCGContext *) ctx;
 
     g_free(s->tb_ctx.tbs);
-    struct uc_struct* uc = s->uc;
+    uc = s->uc;
-    ARMCPU* cpu = (ARMCPU*) uc->cpu;
+    cpu = (ARMCPU*) uc->cpu;
     g_free(cpu->cpreg_indexes);
     g_free(cpu->cpreg_values);
     g_free(cpu->cpreg_vmstate_indexes);
@@ -37,8 +39,8 @@ void arm_release(void* ctx)
 
 void arm_reg_reset(struct uc_struct *uc)
 {
-    (void)uc;
     CPUArchState *env;
+    (void)uc;
 
     env = uc->cpu->env_ptr;
     memset(env->regs, 0, sizeof(env->regs));

qemu/util/oslib-win32.c

@@ -34,7 +34,11 @@
 #include "sysemu/sysemu.h"
 
 /* this must come after including "trace.h" */
+/* The pragmas are to fix this issue: https://connect.microsoft.com/VisualStudio/feedback/details/976983 */
+#pragma warning(push)
+#pragma warning(disable : 4091)
 #include <shlobj.h>
+#pragma warning(pop)
 
 void *qemu_oom_check(void *ptr)
 {