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target/arm: Add state for the ARMv8.3-PAuth extension

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Add storage space for the 5 encryption keys.

Backports commit 991ad91b6a1f09a6ad62b6e6da78d83b548daec7 from qemu
This commit is contained in:
Richard Henderson 2019-01-22 15:11:30 -05:00 committed by Lioncash
parent f2682ff309
commit 8ef39cc2d5
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 29 additions and 1 deletions
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30
qemu/target/arm/cpu.h
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@ -192,11 +192,16 @@ typedef struct ARMVectorReg {
uint64_t QEMU_ALIGNED(16, d[2 * ARM_MAX_VQ]);
} ARMVectorReg;
/* In AArch32 mode, predicate registers do not exist at all. */
#ifdef TARGET_AARCH64
/* In AArch32 mode, predicate registers do not exist at all. */
typedef struct ARMPredicateReg {
uint64_t QEMU_ALIGNED(16, p[2 * ARM_MAX_VQ / 8]);
} ARMPredicateReg;
/* In AArch32 mode, PAC keys do not exist at all. */
typedef struct ARMPACKey {
uint64_t lo, hi;
} ARMPACKey;
#endif
@ -596,6 +601,14 @@ typedef struct CPUARMState {
uint32_t cregs[16];
} iwmmxt;
#ifdef TARGET_AARCH64
ARMPACKey apia_key;
ARMPACKey apib_key;
ARMPACKey apda_key;
ARMPACKey apdb_key;
ARMPACKey apga_key;
#endif
#if defined(CONFIG_USER_ONLY)
/* For usermode syscall translation. */
int eabi;
@ -3248,6 +3261,21 @@ static inline bool isar_feature_aa64_fcma(const ARMISARegisters *id)
return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FCMA) != 0;
}
static inline bool isar_feature_aa64_pauth(const ARMISARegisters *id)
{
/*
* Note that while QEMU will only implement the architected algorithm
* QARMA, and thus APA+GPA, the host cpu for kvm may use implementation
* defined algorithms, and thus API+GPI, and this predicate controls
* migration of the 128-bit keys.
*/
return (id->id_aa64isar1 &
(FIELD_DP64(0, ID_AA64ISAR1, APA, 0xf) |
FIELD_DP64(0, ID_AA64ISAR1, API, 0xf) |
FIELD_DP64(0, ID_AA64ISAR1, GPA, 0xf) |
FIELD_DP64(0, ID_AA64ISAR1, GPI, 0xf))) != 0;
}
static inline bool isar_feature_aa64_fp16(const ARMISARegisters *id)
{
/* We always set the AdvSIMD and FP fields identically wrt FP16. */