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target/arm: Honor the HCR_EL2.TACR bit
This bit traps EL1 access to the auxiliary control registers. Backports commit 9960237769ada2faaaf1898b96da7a55e1691cf4 from qemu
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@ -393,6 +393,16 @@ static CPAccessResult access_tsw(CPUARMState *env, const ARMCPRegInfo *ri,
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return CP_ACCESS_OK;
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}
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/* Check for traps from EL1 due to HCR_EL2.TACR. */
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static CPAccessResult access_tacr(CPUARMState *env, const ARMCPRegInfo *ri,
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bool isread)
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{
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if (arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_TACR)) {
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return CP_ACCESS_TRAP_EL2;
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}
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return CP_ACCESS_OK;
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}
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static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
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{
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ARMCPU *cpu = env_archcpu(env);
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@ -6762,8 +6772,8 @@ static const ARMCPRegInfo ats1cp_reginfo[] = {
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static const ARMCPRegInfo actlr2_hactlr2_reginfo[] = {
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{ .name = "ACTLR2", .state = ARM_CP_STATE_AA32,
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.cp = 15, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 3,
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.access = PL1_RW, .type = ARM_CP_CONST,
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.resetvalue = 0 },
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.access = PL1_RW, .accessfn = access_tacr,
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.type = ARM_CP_CONST, .resetvalue = 0 },
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{ .name = "HACTLR2", .state = ARM_CP_STATE_AA32,
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.cp = 15, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 3,
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.access = PL2_RW, .type = ARM_CP_CONST,
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@ -7518,8 +7528,8 @@ void register_cp_regs_for_features(ARMCPU *cpu)
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ARMCPRegInfo auxcr_reginfo[] = {
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{ .name = "ACTLR_EL1", .state = ARM_CP_STATE_BOTH,
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.opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 1,
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.access = PL1_RW, .type = ARM_CP_CONST,
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.resetvalue = cpu->reset_auxcr },
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.access = PL1_RW, .accessfn = access_tacr,
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.type = ARM_CP_CONST, .resetvalue = cpu->reset_auxcr },
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{ .name = "ACTLR_EL2", .state = ARM_CP_STATE_BOTH,
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.opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 1,
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.access = PL2_RW, .type = ARM_CP_CONST,
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