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target/i386: move cpu_tmp1_i64 to DisasContext

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Backports commit 776678b2961848a80387509c433dc04b0f761592 from qemu
This commit is contained in:
Emilio G. Cota 2018-10-04 03:59:11 -04:00 committed by Lioncash
parent 04530acab2
commit 90e189ca24
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 60 additions and 69 deletions
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129
qemu/target/i386/translate.c
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@ -127,6 +127,7 @@ typedef struct DisasContext {
TCGv_ptr ptr1;
TCGv_i32 tmp2_i32;
TCGv_i32 tmp3_i32;
TCGv_i64 tmp1_i64;
sigjmp_buf jmpbuf;
struct uc_struct *uc;
@ -2293,16 +2294,15 @@ static void gen_bndck(CPUX86State *env, DisasContext *s, int modrm,
TCGCond cond, TCGv_i64 bndv)
{
TCGContext *tcg_ctx = s->uc->tcg_ctx;
TCGv_i64 cpu_tmp1_i64 = tcg_ctx->cpu_tmp1_i64;
TCGv ea = gen_lea_modrm_1(s, gen_lea_modrm_0(env, s, modrm));
tcg_gen_extu_tl_i64(tcg_ctx, cpu_tmp1_i64, ea);
tcg_gen_extu_tl_i64(tcg_ctx, s->tmp1_i64, ea);
if (!CODE64(s)) {
tcg_gen_ext32u_i64(tcg_ctx, cpu_tmp1_i64, cpu_tmp1_i64);
tcg_gen_ext32u_i64(tcg_ctx, s->tmp1_i64, s->tmp1_i64);
}
tcg_gen_setcond_i64(tcg_ctx, cond, cpu_tmp1_i64, cpu_tmp1_i64, bndv);
tcg_gen_extrl_i64_i32(tcg_ctx, s->tmp2_i32, cpu_tmp1_i64);
tcg_gen_setcond_i64(tcg_ctx, cond, s->tmp1_i64, s->tmp1_i64, bndv);
tcg_gen_extrl_i64_i32(tcg_ctx, s->tmp2_i32, s->tmp1_i64);
gen_helper_bndck(tcg_ctx, tcg_ctx->cpu_env, s->tmp2_i32);
}
@ -2875,65 +2875,59 @@ static void gen_jmp(DisasContext *s, target_ulong eip)
static inline void gen_ldq_env_A0(DisasContext *s, int offset)
{
TCGContext *tcg_ctx = s->uc->tcg_ctx;
TCGv_i64 cpu_tmp1_i64 = tcg_ctx->cpu_tmp1_i64;
tcg_gen_qemu_ld_i64(s->uc, cpu_tmp1_i64, s->A0, s->mem_index, MO_LEQ);
tcg_gen_st_i64(tcg_ctx, cpu_tmp1_i64, tcg_ctx->cpu_env, offset);
tcg_gen_qemu_ld_i64(s->uc, s->tmp1_i64, s->A0, s->mem_index, MO_LEQ);
tcg_gen_st_i64(tcg_ctx, s->tmp1_i64, tcg_ctx->cpu_env, offset);
}
static inline void gen_stq_env_A0(DisasContext *s, int offset)
{
TCGContext *tcg_ctx = s->uc->tcg_ctx;
TCGv_i64 cpu_tmp1_i64 = tcg_ctx->cpu_tmp1_i64;
tcg_gen_ld_i64(tcg_ctx, cpu_tmp1_i64, tcg_ctx->cpu_env, offset);
tcg_gen_qemu_st_i64(s->uc, cpu_tmp1_i64, s->A0, s->mem_index, MO_LEQ);
tcg_gen_ld_i64(tcg_ctx, s->tmp1_i64, tcg_ctx->cpu_env, offset);
tcg_gen_qemu_st_i64(s->uc, s->tmp1_i64, s->A0, s->mem_index, MO_LEQ);
}
static inline void gen_ldo_env_A0(DisasContext *s, int offset)
{
int mem_index = s->mem_index;
TCGContext *tcg_ctx = s->uc->tcg_ctx;
TCGv_i64 cpu_tmp1_i64 = tcg_ctx->cpu_tmp1_i64;
tcg_gen_qemu_ld_i64(s->uc, cpu_tmp1_i64, s->A0, mem_index, MO_LEQ);
tcg_gen_st_i64(tcg_ctx, cpu_tmp1_i64, tcg_ctx->cpu_env, offset + offsetof(ZMMReg, ZMM_Q(0)));
tcg_gen_qemu_ld_i64(s->uc, s->tmp1_i64, s->A0, mem_index, MO_LEQ);
tcg_gen_st_i64(tcg_ctx, s->tmp1_i64, tcg_ctx->cpu_env, offset + offsetof(ZMMReg, ZMM_Q(0)));
tcg_gen_addi_tl(tcg_ctx, s->tmp0, s->A0, 8);
tcg_gen_qemu_ld_i64(s->uc, cpu_tmp1_i64, s->tmp0, mem_index, MO_LEQ);
tcg_gen_st_i64(tcg_ctx, cpu_tmp1_i64, tcg_ctx->cpu_env, offset + offsetof(ZMMReg, ZMM_Q(1)));
tcg_gen_qemu_ld_i64(s->uc, s->tmp1_i64, s->tmp0, mem_index, MO_LEQ);
tcg_gen_st_i64(tcg_ctx, s->tmp1_i64, tcg_ctx->cpu_env, offset + offsetof(ZMMReg, ZMM_Q(1)));
}
static inline void gen_sto_env_A0(DisasContext *s, int offset)
{
int mem_index = s->mem_index;
TCGContext *tcg_ctx = s->uc->tcg_ctx;
TCGv_i64 cpu_tmp1_i64 = tcg_ctx->cpu_tmp1_i64;
tcg_gen_ld_i64(tcg_ctx, cpu_tmp1_i64, tcg_ctx->cpu_env, offset + offsetof(ZMMReg, ZMM_Q(0)));
tcg_gen_qemu_st_i64(s->uc, cpu_tmp1_i64, s->A0, mem_index, MO_LEQ);
tcg_gen_ld_i64(tcg_ctx, s->tmp1_i64, tcg_ctx->cpu_env, offset + offsetof(ZMMReg, ZMM_Q(0)));
tcg_gen_qemu_st_i64(s->uc, s->tmp1_i64, s->A0, mem_index, MO_LEQ);
tcg_gen_addi_tl(tcg_ctx, s->tmp0, s->A0, 8);
tcg_gen_ld_i64(tcg_ctx, cpu_tmp1_i64, tcg_ctx->cpu_env, offset + offsetof(ZMMReg, ZMM_Q(1)));
tcg_gen_qemu_st_i64(s->uc, cpu_tmp1_i64, s->tmp0, mem_index, MO_LEQ);
tcg_gen_ld_i64(tcg_ctx, s->tmp1_i64, tcg_ctx->cpu_env, offset + offsetof(ZMMReg, ZMM_Q(1)));
tcg_gen_qemu_st_i64(s->uc, s->tmp1_i64, s->tmp0, mem_index, MO_LEQ);
}
static inline void gen_op_movo(DisasContext *s, int d_offset, int s_offset)
{
TCGContext *tcg_ctx = s->uc->tcg_ctx;
TCGv_i64 cpu_tmp1_i64 = tcg_ctx->cpu_tmp1_i64;
tcg_gen_ld_i64(tcg_ctx, cpu_tmp1_i64, tcg_ctx->cpu_env, s_offset);
tcg_gen_st_i64(tcg_ctx, cpu_tmp1_i64, tcg_ctx->cpu_env, d_offset);
tcg_gen_ld_i64(tcg_ctx, cpu_tmp1_i64, tcg_ctx->cpu_env, s_offset + 8);
tcg_gen_st_i64(tcg_ctx, cpu_tmp1_i64, tcg_ctx->cpu_env, d_offset + 8);
tcg_gen_ld_i64(tcg_ctx, s->tmp1_i64, tcg_ctx->cpu_env, s_offset);
tcg_gen_st_i64(tcg_ctx, s->tmp1_i64, tcg_ctx->cpu_env, d_offset);
tcg_gen_ld_i64(tcg_ctx, s->tmp1_i64, tcg_ctx->cpu_env, s_offset + 8);
tcg_gen_st_i64(tcg_ctx, s->tmp1_i64, tcg_ctx->cpu_env, d_offset + 8);
}
static inline void gen_op_movq(DisasContext *s, int d_offset, int s_offset)
{
TCGContext *tcg_ctx = s->uc->tcg_ctx;
TCGv_i64 cpu_tmp1_i64 = tcg_ctx->cpu_tmp1_i64;
tcg_gen_ld_i64(tcg_ctx, cpu_tmp1_i64, tcg_ctx->cpu_env, s_offset);
tcg_gen_st_i64(tcg_ctx, cpu_tmp1_i64, tcg_ctx->cpu_env, d_offset);
tcg_gen_ld_i64(tcg_ctx, s->tmp1_i64, tcg_ctx->cpu_env, s_offset);
tcg_gen_st_i64(tcg_ctx, s->tmp1_i64, tcg_ctx->cpu_env, d_offset);
}
static inline void gen_op_movl(DisasContext *s, int d_offset, int s_offset)
@ -2947,10 +2941,9 @@ static inline void gen_op_movl(DisasContext *s, int d_offset, int s_offset)
static inline void gen_op_movq_env_0(DisasContext *s, int d_offset)
{
TCGContext *tcg_ctx = s->uc->tcg_ctx;
TCGv_i64 cpu_tmp1_i64 = tcg_ctx->cpu_tmp1_i64;
tcg_gen_movi_i64(tcg_ctx, cpu_tmp1_i64, 0);
tcg_gen_st_i64(tcg_ctx, cpu_tmp1_i64, tcg_ctx->cpu_env, d_offset);
tcg_gen_movi_i64(tcg_ctx, s->tmp1_i64, 0);
tcg_gen_st_i64(tcg_ctx, s->tmp1_i64, tcg_ctx->cpu_env, d_offset);
}
typedef void (*SSEFunc_i_ep)(TCGContext *s, TCGv_i32 val, TCGv_ptr env, TCGv_ptr reg);
@ -3485,7 +3478,6 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
TCGMemOp ot;
TCGContext *tcg_ctx = s->uc->tcg_ctx;
TCGv_ptr cpu_env = tcg_ctx->cpu_env;
TCGv_i64 cpu_tmp1_i64 = tcg_ctx->cpu_tmp1_i64;
TCGv cpu_cc_dst = tcg_ctx->cpu_cc_dst;
TCGv cpu_cc_src = tcg_ctx->cpu_cc_src;
TCGv cpu_cc_src2 = tcg_ctx->cpu_cc_src2;
@ -3630,9 +3622,9 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
gen_ldq_env_A0(s, offsetof(CPUX86State, fpregs[reg].mmx));
} else {
rm = (modrm & 7);
tcg_gen_ld_i64(tcg_ctx, cpu_tmp1_i64, cpu_env,
tcg_gen_ld_i64(tcg_ctx, s->tmp1_i64, cpu_env,
offsetof(CPUX86State,fpregs[rm].mmx));
tcg_gen_st_i64(tcg_ctx, cpu_tmp1_i64, cpu_env,
tcg_gen_st_i64(tcg_ctx, s->tmp1_i64, cpu_env,
offsetof(CPUX86State,fpregs[reg].mmx));
}
break;
@ -4612,13 +4604,13 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
}
} else { /* pextrq */
#ifdef TARGET_X86_64
tcg_gen_ld_i64(tcg_ctx, cpu_tmp1_i64, cpu_env,
tcg_gen_ld_i64(tcg_ctx, s->tmp1_i64, cpu_env,
offsetof(CPUX86State,
xmm_regs[reg].ZMM_Q(val & 1)));
if (mod == 3) {
tcg_gen_mov_i64(tcg_ctx, cpu_regs[rm], cpu_tmp1_i64);
tcg_gen_mov_i64(tcg_ctx, cpu_regs[rm], s->tmp1_i64);
} else {
tcg_gen_qemu_st_i64(s->uc, cpu_tmp1_i64, s->A0,
tcg_gen_qemu_st_i64(s->uc, s->tmp1_i64, s->A0,
s->mem_index, MO_LEQ);
}
#else
@ -4689,12 +4681,12 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
} else { /* pinsrq */
#ifdef TARGET_X86_64
if (mod == 3) {
gen_op_mov_v_reg(s, ot, cpu_tmp1_i64, rm);
gen_op_mov_v_reg(s, ot, s->tmp1_i64, rm);
} else {
tcg_gen_qemu_ld_i64(s->uc, cpu_tmp1_i64, s->A0,
tcg_gen_qemu_ld_i64(s->uc, s->tmp1_i64, s->A0,
s->mem_index, MO_LEQ);
}
tcg_gen_st_i64(tcg_ctx, cpu_tmp1_i64, cpu_env,
tcg_gen_st_i64(tcg_ctx, s->tmp1_i64, cpu_env,
offsetof(CPUX86State,
xmm_regs[reg].ZMM_Q(val & 1)));
#else
@ -4944,7 +4936,6 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
target_ulong pc_start = s->base.pc_next;
TCGContext *tcg_ctx = s->uc->tcg_ctx;
TCGv_ptr cpu_env = tcg_ctx->cpu_env;
TCGv_i64 cpu_tmp1_i64 = tcg_ctx->cpu_tmp1_i64;
TCGv cpu_cc_dst = tcg_ctx->cpu_cc_dst;
TCGv cpu_cc_src = tcg_ctx->cpu_cc_src;
TCGv *cpu_regs = tcg_ctx->cpu_regs;
@ -6379,9 +6370,9 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
gen_helper_fildl_FT0(tcg_ctx, cpu_env, s->tmp2_i32);
break;
case 2:
tcg_gen_qemu_ld_i64(s->uc, cpu_tmp1_i64, s->A0,
tcg_gen_qemu_ld_i64(s->uc, s->tmp1_i64, s->A0,
s->mem_index, MO_LEQ);
gen_helper_fldl_FT0(tcg_ctx, cpu_env, cpu_tmp1_i64);
gen_helper_fldl_FT0(tcg_ctx, cpu_env, s->tmp1_i64);
break;
case 3:
default:
@ -6418,9 +6409,9 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
gen_helper_fildl_ST0(tcg_ctx, cpu_env, s->tmp2_i32);
break;
case 2:
tcg_gen_qemu_ld_i64(s->uc, cpu_tmp1_i64, s->A0,
tcg_gen_qemu_ld_i64(s->uc, s->tmp1_i64, s->A0,
s->mem_index, MO_LEQ);
gen_helper_fldl_ST0(tcg_ctx, cpu_env, cpu_tmp1_i64);
gen_helper_fldl_ST0(tcg_ctx, cpu_env, s->tmp1_i64);
break;
case 3:
default:
@ -6439,8 +6430,8 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
s->mem_index, MO_LEUL);
break;
case 2:
gen_helper_fisttll_ST0(tcg_ctx, cpu_tmp1_i64, cpu_env);
tcg_gen_qemu_st_i64(s->uc, cpu_tmp1_i64, s->A0,
gen_helper_fisttll_ST0(tcg_ctx, s->tmp1_i64, cpu_env);
tcg_gen_qemu_st_i64(s->uc, s->tmp1_i64, s->A0,
s->mem_index, MO_LEQ);
break;
case 3:
@ -6465,8 +6456,8 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
s->mem_index, MO_LEUL);
break;
case 2:
gen_helper_fstl_ST0(tcg_ctx, cpu_tmp1_i64, cpu_env);
tcg_gen_qemu_st_i64(s->uc, cpu_tmp1_i64, s->A0,
gen_helper_fstl_ST0(tcg_ctx, s->tmp1_i64, cpu_env);
tcg_gen_qemu_st_i64(s->uc, s->tmp1_i64, s->A0,
s->mem_index, MO_LEQ);
break;
case 3:
@ -6535,13 +6526,13 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
}
else if(op == 0x3d) /* fildll */
{
tcg_gen_qemu_ld_i64(s->uc, cpu_tmp1_i64, s->A0, s->mem_index, MO_LEQ);
gen_helper_fildll_ST0(tcg_ctx, cpu_env, cpu_tmp1_i64);
tcg_gen_qemu_ld_i64(s->uc, s->tmp1_i64, s->A0, s->mem_index, MO_LEQ);
gen_helper_fildll_ST0(tcg_ctx, cpu_env, s->tmp1_i64);
}
else if(op == 0x3f) /* fistpll */
{
gen_helper_fistll_ST0(tcg_ctx, cpu_tmp1_i64, cpu_env);
tcg_gen_qemu_st_i64(s->uc, cpu_tmp1_i64, s->A0, s->mem_index, MO_LEQ);
gen_helper_fistll_ST0(tcg_ctx, s->tmp1_i64, cpu_env);
tcg_gen_qemu_st_i64(s->uc, s->tmp1_i64, s->A0, s->mem_index, MO_LEQ);
gen_helper_fpop(tcg_ctx, cpu_env);
}
else
@ -7916,8 +7907,8 @@ case 0x101:
goto illegal_op;
}
tcg_gen_trunc_tl_i32(tcg_ctx, s->tmp2_i32, cpu_regs[R_ECX]);
gen_helper_xgetbv(tcg_ctx, cpu_tmp1_i64, cpu_env, s->tmp2_i32);
tcg_gen_extr_i64_tl(tcg_ctx, cpu_regs[R_EAX], cpu_regs[R_EDX], cpu_tmp1_i64);
gen_helper_xgetbv(tcg_ctx, s->tmp1_i64, cpu_env, s->tmp2_i32);
tcg_gen_extr_i64_tl(tcg_ctx, cpu_regs[R_EAX], cpu_regs[R_EDX], s->tmp1_i64);
break;
case 0xd1: /* xsetbv */
@ -7930,10 +7921,10 @@ case 0x101:
gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
break;
}
tcg_gen_concat_tl_i64(tcg_ctx, cpu_tmp1_i64, cpu_regs[R_EAX],
tcg_gen_concat_tl_i64(tcg_ctx, s->tmp1_i64, cpu_regs[R_EAX],
cpu_regs[R_EDX]);
tcg_gen_trunc_tl_i32(tcg_ctx, s->tmp2_i32, cpu_regs[R_ECX]);
gen_helper_xsetbv(tcg_ctx, cpu_env, s->tmp2_i32, cpu_tmp1_i64);
gen_helper_xsetbv(tcg_ctx, cpu_env, s->tmp2_i32, s->tmp1_i64);
/* End TB because translation flags may change. */
gen_jmp_im(s, s->pc - s->cs_base);
gen_eob(s);
@ -8097,17 +8088,17 @@ case 0x101:
goto illegal_op;
}
tcg_gen_trunc_tl_i32(tcg_ctx, s->tmp2_i32, cpu_regs[R_ECX]);
gen_helper_rdpkru(tcg_ctx, cpu_tmp1_i64, cpu_env, s->tmp2_i32);
tcg_gen_extr_i64_tl(tcg_ctx, cpu_regs[R_EAX], cpu_regs[R_EDX], cpu_tmp1_i64);
gen_helper_rdpkru(tcg_ctx, s->tmp1_i64, cpu_env, s->tmp2_i32);
tcg_gen_extr_i64_tl(tcg_ctx, cpu_regs[R_EAX], cpu_regs[R_EDX], s->tmp1_i64);
break;
case 0xef: /* wrpkru */
if (prefixes & PREFIX_LOCK) {
goto illegal_op;
}
tcg_gen_concat_tl_i64(tcg_ctx, cpu_tmp1_i64, cpu_regs[R_EAX],
tcg_gen_concat_tl_i64(tcg_ctx, s->tmp1_i64, cpu_regs[R_EAX],
cpu_regs[R_EDX]);
tcg_gen_trunc_tl_i32(tcg_ctx, s->tmp2_i32, cpu_regs[R_ECX]);
gen_helper_wrpkru(tcg_ctx, cpu_env, s->tmp2_i32, cpu_tmp1_i64);
gen_helper_wrpkru(tcg_ctx, cpu_env, s->tmp2_i32, s->tmp1_i64);
break;
CASE_MODRM_OP(6): /* lmsw */
if (s->cpl != 0) {
@ -8688,9 +8679,9 @@ case 0x101:
goto illegal_op;
}
gen_lea_modrm(env, s, modrm);
tcg_gen_concat_tl_i64(tcg_ctx, cpu_tmp1_i64, cpu_regs[R_EAX],
tcg_gen_concat_tl_i64(tcg_ctx, s->tmp1_i64, cpu_regs[R_EAX],
cpu_regs[R_EDX]);
gen_helper_xsave(tcg_ctx, cpu_env, s->A0, cpu_tmp1_i64);
gen_helper_xsave(tcg_ctx, cpu_env, s->A0, s->tmp1_i64);
break;
CASE_MODRM_MEM_OP(5): /* xrstor */
@ -8700,9 +8691,9 @@ case 0x101:
goto illegal_op;
}
gen_lea_modrm(env, s, modrm);
tcg_gen_concat_tl_i64(tcg_ctx, cpu_tmp1_i64, cpu_regs[R_EAX],
tcg_gen_concat_tl_i64(tcg_ctx, s->tmp1_i64, cpu_regs[R_EAX],
cpu_regs[R_EDX]);
gen_helper_xrstor(tcg_ctx, cpu_env, s->A0, cpu_tmp1_i64);
gen_helper_xrstor(tcg_ctx, cpu_env, s->A0, s->tmp1_i64);
/* XRSTOR is how MPX is enabled, which changes how
we translate. Thus we need to end the TB. */
gen_update_cc_op(s);
@ -8728,9 +8719,9 @@ case 0x101:
goto illegal_op;
}
gen_lea_modrm(env, s, modrm);
tcg_gen_concat_tl_i64(tcg_ctx, cpu_tmp1_i64, cpu_regs[R_EAX],
tcg_gen_concat_tl_i64(tcg_ctx, s->tmp1_i64, cpu_regs[R_EAX],
cpu_regs[R_EDX]);
gen_helper_xsaveopt(tcg_ctx, cpu_env, s->A0, cpu_tmp1_i64);
gen_helper_xsaveopt(tcg_ctx, cpu_env, s->A0, s->tmp1_i64);
}
break;
@ -9118,7 +9109,7 @@ static void i386_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu)
dc->tmp0 = tcg_temp_new(tcg_ctx);
dc->tmp4 = tcg_temp_new(tcg_ctx);
tcg_ctx->cpu_tmp1_i64 = tcg_temp_new_i64(tcg_ctx);
dc->tmp1_i64 = tcg_temp_new_i64(tcg_ctx);
dc->tmp2_i32 = tcg_temp_new_i32(tcg_ctx);
dc->tmp3_i32 = tcg_temp_new_i32(tcg_ctx);
dc->ptr0 = tcg_temp_new_ptr(tcg_ctx);