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target-arm: Move TLBI ALLE1/ALLE1IS definitions into numeric order

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Move the two regdefs for TLBI ALLE1 and TLBI ALLE1IS down so that the
whole set of AArch64 TLBI regdefs is arranged in numeric order.

Backports commit 83ddf975777cc23337b7ef92e83b1b9c949396f3 from qemu
This commit is contained in:
Peter Maydell 2018-02-15 09:38:42 -05:00 committed by Lioncash
parent 6e94bda144
commit 91262f721e
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 6 additions and 6 deletions
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12
qemu/target-arm/helper.c
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@ -2363,12 +2363,6 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
{ "DC_CISW", 0,7,14, 1,0,2, ARM_CP_STATE_AA64,
ARM_CP_NOP, PL1_W, },
/* TLBI operations */
{ "TLBI_ALLE1", 0,8,7, 1,4,4, ARM_CP_STATE_AA64, ARM_CP_NO_RAW,
PL2_W, 0, NULL, 0, 0, {0, 0},
NULL, NULL, tlbiall_write },
{ "TLBI_ALLE1IS", 0,8,3, 1,4,4, ARM_CP_STATE_AA64, ARM_CP_NO_RAW,
PL2_W, 0, NULL, 0, 0, {0, 0},
NULL, NULL, tlbiall_is_write },
{ "TLBI_VMALLE1IS", 0,8,3, 1,0,0, ARM_CP_STATE_AA64,
ARM_CP_NO_RAW, PL1_W, 0, NULL, 0, 0, {0, 0},
NULL, NULL, tlbiall_is_write },
@ -2405,6 +2399,12 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
{ "TLBI_VAALE1", 0,8,7, 1,0,7, ARM_CP_STATE_AA64,
ARM_CP_NO_RAW, PL1_W, 0, NULL, 0, 0, {0, 0},
NULL, NULL, tlbi_aa64_vaa_write },
{ "TLBI_ALLE1IS", 0,8,3, 1,4,4, ARM_CP_STATE_AA64, ARM_CP_NO_RAW,
PL2_W, 0, NULL, 0, 0, {0, 0},
NULL, NULL, tlbiall_is_write },
{ "TLBI_ALLE1", 0,8,7, 1,4,4, ARM_CP_STATE_AA64, ARM_CP_NO_RAW,
PL2_W, 0, NULL, 0, 0, {0, 0},
NULL, NULL, tlbiall_write },
#ifndef CONFIG_USER_ONLY
/* 64 bit address translation operations */
{ "AT_S1E1R", 0,7,8, 1,0,0, ARM_CP_STATE_AA64,