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target/mips: Move MUL, S32M2I, S32I2M handling out of main MXU switch

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Move MUL, S32M2I, S32I2M handling out of switch. These are all
instructions that do not depend on MXU_EN flag of MXU_CR.

Backports commit 87860df5511b972f0234a6b2cfaad5227c79b6b4 from qemu
This commit is contained in:
Aleksandar Markovic 2018-11-11 06:12:30 -05:00 committed by Lioncash
parent 3862cd205d
commit 914c0cea7c
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 23 additions and 18 deletions
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41
qemu/target/mips/translate.c
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@ -25148,6 +25148,29 @@ static void decode_opc_mxu(CPUMIPSState *env, DisasContext *ctx)
*/
uint32_t opcode = extract32(ctx->opcode, 0, 6);
if (opcode == OPC__MXU_MUL) {
uint32_t rs, rt, rd, op1;
rs = extract32(ctx->opcode, 21, 5);
rt = extract32(ctx->opcode, 16, 5);
rd = extract32(ctx->opcode, 11, 5);
op1 = MASK_SPECIAL2(ctx->opcode);
gen_arith(ctx, op1, rd, rs, rt);
return;
}
if (opcode == OPC_MXU_S32M2I) {
gen_mxu_s32m2i(ctx);
return;
}
if (opcode == OPC_MXU_S32I2M) {
gen_mxu_s32i2m(ctx);
return;
}
switch (opcode) {
case OPC_MXU_S32MADD:
/* TODO: Implement emulation of S32MADD instruction. */
@ -25159,18 +25182,6 @@ static void decode_opc_mxu(CPUMIPSState *env, DisasContext *ctx)
MIPS_INVAL("OPC_MXU_S32MADDU");
generate_exception_end(ctx, EXCP_RI);
break;
case OPC__MXU_MUL: /* 0x2 - unused in MXU specs */
{
uint32_t rs, rt, rd, op1;
rs = extract32(ctx->opcode, 21, 5);
rt = extract32(ctx->opcode, 16, 5);
rd = extract32(ctx->opcode, 11, 5);
op1 = MASK_SPECIAL2(ctx->opcode);
gen_arith(ctx, op1, rd, rs, rt);
}
break;
case OPC_MXU__POOL00:
decode_opc_mxu__pool00(env, ctx);
break;
@ -25322,12 +25333,6 @@ static void decode_opc_mxu(CPUMIPSState *env, DisasContext *ctx)
MIPS_INVAL("OPC_MXU_S16SDI");
generate_exception_end(ctx, EXCP_RI);
break;
case OPC_MXU_S32M2I:
gen_mxu_s32m2i(ctx);
break;
case OPC_MXU_S32I2M:
gen_mxu_s32i2m(ctx);
break;
case OPC_MXU_D32SLL:
/* TODO: Implement emulation of D32SLL instruction. */
MIPS_INVAL("OPC_MXU_D32SLL");