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target/arm: Convert T16 add, compare, move (two high registers)
Backports commit 90aa042115a0fe39fe4cb3bcae4c4f728e2f3fdb from qemu
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@ -146,6 +146,16 @@ CMP_xri 00101 ... ........ @arith_1i s=1
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ADD_rri 00110 ... ........ @arith_1i %s
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SUB_rri 00111 ... ........ @arith_1i %s
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# Add, compare, move (two high registers)
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%reg_0_7 7:1 0:3
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@addsub_2h .... .... . rm:4 ... \
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&s_rrr_shi rd=%reg_0_7 rn=%reg_0_7 shim=0 shty=0
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ADD_rrri 0100 0100 . .... ... @addsub_2h s=0
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CMP_xrri 0100 0101 . .... ... @addsub_2h s=1
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MOV_rxri 0100 0110 . .... ... @addsub_2h s=0
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# Branch and exchange
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@branchr .... .... . rm:4 ... &r
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@ -11097,55 +11097,11 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
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store_reg(s, rd, tmp);
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break;
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}
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if (insn & (1 << 10)) {
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/* 0b0100_01xx_xxxx_xxxx
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* - data processing extended, branch and exchange
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*/
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rd = (insn & 7) | ((insn >> 4) & 8);
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rm = (insn >> 3) & 0xf;
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op = (insn >> 8) & 3;
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switch (op) {
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case 0: /* add */
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tmp = load_reg(s, rd);
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tmp2 = load_reg(s, rm);
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tcg_gen_add_i32(tcg_ctx, tmp, tmp, tmp2);
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tcg_temp_free_i32(tcg_ctx, tmp2);
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if (rd == 13) {
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/* ADD SP, SP, reg */
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store_sp_checked(s, tmp);
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} else {
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store_reg(s, rd, tmp);
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}
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break;
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case 1: /* cmp */
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tmp = load_reg(s, rd);
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tmp2 = load_reg(s, rm);
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gen_sub_CC(s, tmp, tmp, tmp2);
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tcg_temp_free_i32(tcg_ctx, tmp2);
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tcg_temp_free_i32(tcg_ctx, tmp);
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break;
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case 2: /* mov/cpy */
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tmp = load_reg(s, rm);
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if (rd == 13) {
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/* MOV SP, reg */
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store_sp_checked(s, tmp);
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} else {
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store_reg(s, rd, tmp);
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}
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break;
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case 3:
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/* 0b0100_0111_xxxx_xxxx
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* - branch [and link] exchange thumb register
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* In decodetree
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*/
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goto illegal_op;
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}
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break;
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}
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/*
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* 0b0100_00xx_xxxx_xxxx
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* - Data-processing (two low registers), in decodetree
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* - Data-processing (two low registers), in decodetree
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* - data processing extended, branch and exchange, in decodetree
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*/
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goto illegal_op;
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