Add MemTxAttrs to the IOTLB

Add a MemTxAttrs field to the IOTLB, and allow target-specific
code to set it via a new tlb_set_page_with_attrs() function;
pass the attributes through to the device when making IO accesses.

Backports commit fadc1cbe85c6b032d5842ec0d19d209f50fcb375 from qemu

qemu/aarch64.h

@@ -149,6 +149,7 @@
 #define tlb_flush tlb_flush_aarch64
 #define tlb_flush_page tlb_flush_page_aarch64
 #define tlb_set_page tlb_set_page_aarch64
+#define tlb_set_page_with_attrs tlb_set_page_with_attrs_aarch64
 #define arm_translate_init arm_translate_init_aarch64
 #define arm_v7m_class_init arm_v7m_class_init_aarch64
 #define arm_v7m_cpu_do_interrupt arm_v7m_cpu_do_interrupt_aarch64

qemu/aarch64eb.h

@@ -149,6 +149,7 @@
 #define tlb_flush tlb_flush_aarch64eb
 #define tlb_flush_page tlb_flush_page_aarch64eb
 #define tlb_set_page tlb_set_page_aarch64eb
+#define tlb_set_page_with_attrs tlb_set_page_with_attrs_aarch64eb
 #define arm_translate_init arm_translate_init_aarch64eb
 #define arm_v7m_class_init arm_v7m_class_init_aarch64eb
 #define arm_v7m_cpu_do_interrupt arm_v7m_cpu_do_interrupt_aarch64eb

qemu/arm.h

@@ -149,6 +149,7 @@
 #define tlb_flush tlb_flush_arm
 #define tlb_flush_page tlb_flush_page_arm
 #define tlb_set_page tlb_set_page_arm
+#define tlb_set_page_with_attrs tlb_set_page_with_attrs_arm
 #define arm_translate_init arm_translate_init_arm
 #define arm_v7m_class_init arm_v7m_class_init_arm
 #define arm_v7m_cpu_do_interrupt arm_v7m_cpu_do_interrupt_arm

qemu/armeb.h

@@ -149,6 +149,7 @@
 #define tlb_flush tlb_flush_armeb
 #define tlb_flush_page tlb_flush_page_armeb
 #define tlb_set_page tlb_set_page_armeb
+#define tlb_set_page_with_attrs tlb_set_page_with_attrs_armeb
 #define arm_translate_init arm_translate_init_armeb
 #define arm_v7m_class_init arm_v7m_class_init_armeb
 #define arm_v7m_cpu_do_interrupt arm_v7m_cpu_do_interrupt_armeb

qemu/cputlb.c

@@ -198,8 +198,8 @@ void tlb_set_dirty(CPUArchState *env, target_ulong vaddr)
 /* Add a new TLB entry. At most one entry for a given virtual address
    is permitted. Only a single TARGET_PAGE_SIZE region is mapped, the
    supplied size is only used by tlb_flush_page.  */
-void tlb_set_page(CPUState *cpu, target_ulong vaddr,
-                  hwaddr paddr, int prot,
+void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr,
+                             hwaddr paddr, MemTxAttrs attrs, int prot,
                              int mmu_idx, target_ulong size)
 {
     CPUArchState *env = cpu->env_ptr;
@@ -250,6 +250,7 @@ void tlb_set_page(CPUState *cpu, target_ulong vaddr,
 
     /* refill the tlb */
     env->iotlb[mmu_idx][index].addr = iotlb - vaddr;
+    env->iotlb[mmu_idx][index].attrs = attrs;
     te->addend = (uintptr_t)(addend - vaddr);
     if (prot & PAGE_READ) {
         te->addr_read = address;
@@ -279,6 +280,17 @@ void tlb_set_page(CPUState *cpu, target_ulong vaddr,
     }
 }
 
+/* Add a new TLB entry, but without specifying the memory
+ * transaction attributes to be used.
+ */
+void tlb_set_page(CPUState *cpu, target_ulong vaddr,
+                  hwaddr paddr, int prot,
+                  int mmu_idx, target_ulong size)
+{
+    tlb_set_page_with_attrs(cpu, vaddr, paddr, MEMTXATTRS_UNSPECIFIED,
+                            prot, mmu_idx, size);
+}
+
 /* NOTE: this function can trigger an exception */
 /* NOTE2: the returned address is not exactly the physical address: it
  * is actually a ram_addr_t (in system mode; the user mode emulation

qemu/header_gen.py

@@ -155,6 +155,7 @@ symbols = (
     'tlb_flush',
     'tlb_flush_page',
     'tlb_set_page',
+    'tlb_set_page_with_attrs',
     'arm_translate_init',
     'arm_v7m_class_init',
     'arm_v7m_cpu_do_interrupt',

qemu/include/exec/cpu-defs.h

@@ -30,6 +30,7 @@
 #ifndef CONFIG_USER_ONLY
 #include "exec/hwaddr.h"
 #endif
+#include "exec/memattrs.h"
 
 #ifndef TARGET_LONG_BITS
 #error TARGET_LONG_BITS must be defined before including this header
@@ -128,6 +129,7 @@ QEMU_BUILD_BUG_ON(sizeof(CPUTLBEntry) != (1 << CPU_TLB_ENTRY_BITS));
  */
 typedef struct CPUIOTLBEntry {
     hwaddr addr;
+    MemTxAttrs attrs;
 } CPUIOTLBEntry;
 
 #define CPU_COMMON_TLB \

qemu/include/exec/exec-all.h

@@ -100,6 +100,9 @@ void tlb_flush(CPUState *cpu, int flush_global);
 void tlb_set_page(CPUState *cpu, target_ulong vaddr,
                   hwaddr paddr, int prot,
                   int mmu_idx, target_ulong size);
+void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr,
+                             hwaddr paddr, MemTxAttrs attrs,
+                             int prot, int mmu_idx, target_ulong size);
 
 void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr);
 

qemu/m68k.h

@@ -149,6 +149,7 @@
 #define tlb_flush tlb_flush_m68k
 #define tlb_flush_page tlb_flush_page_m68k
 #define tlb_set_page tlb_set_page_m68k
+#define tlb_set_page_with_attrs tlb_set_page_with_attrs_m68k
 #define arm_translate_init arm_translate_init_m68k
 #define arm_v7m_class_init arm_v7m_class_init_m68k
 #define arm_v7m_cpu_do_interrupt arm_v7m_cpu_do_interrupt_m68k

qemu/mips.h

@@ -149,6 +149,7 @@
 #define tlb_flush tlb_flush_mips
 #define tlb_flush_page tlb_flush_page_mips
 #define tlb_set_page tlb_set_page_mips
+#define tlb_set_page_with_attrs tlb_set_page_with_attrs_mips
 #define arm_translate_init arm_translate_init_mips
 #define arm_v7m_class_init arm_v7m_class_init_mips
 #define arm_v7m_cpu_do_interrupt arm_v7m_cpu_do_interrupt_mips

qemu/mips64.h

@@ -149,6 +149,7 @@
 #define tlb_flush tlb_flush_mips64
 #define tlb_flush_page tlb_flush_page_mips64
 #define tlb_set_page tlb_set_page_mips64
+#define tlb_set_page_with_attrs tlb_set_page_with_attrs_mips64
 #define arm_translate_init arm_translate_init_mips64
 #define arm_v7m_class_init arm_v7m_class_init_mips64
 #define arm_v7m_cpu_do_interrupt arm_v7m_cpu_do_interrupt_mips64

qemu/mips64el.h

@@ -149,6 +149,7 @@
 #define tlb_flush tlb_flush_mips64el
 #define tlb_flush_page tlb_flush_page_mips64el
 #define tlb_set_page tlb_set_page_mips64el
+#define tlb_set_page_with_attrs tlb_set_page_with_attrs_mips64el
 #define arm_translate_init arm_translate_init_mips64el
 #define arm_v7m_class_init arm_v7m_class_init_mips64el
 #define arm_v7m_cpu_do_interrupt arm_v7m_cpu_do_interrupt_mips64el

qemu/mipsel.h

@@ -149,6 +149,7 @@
 #define tlb_flush tlb_flush_mipsel
 #define tlb_flush_page tlb_flush_page_mipsel
 #define tlb_set_page tlb_set_page_mipsel
+#define tlb_set_page_with_attrs tlb_set_page_with_attrs_mipsel
 #define arm_translate_init arm_translate_init_mipsel
 #define arm_v7m_class_init arm_v7m_class_init_mipsel
 #define arm_v7m_cpu_do_interrupt arm_v7m_cpu_do_interrupt_mipsel

qemu/powerpc.h

@@ -149,6 +149,7 @@
 #define tlb_flush tlb_flush_powerpc
 #define tlb_flush_page tlb_flush_page_powerpc
 #define tlb_set_page tlb_set_page_powerpc
+#define tlb_set_page_with_attrs tlb_set_page_with_attrs_powerpc
 #define arm_translate_init arm_translate_init_powerpc
 #define arm_v7m_class_init arm_v7m_class_init_powerpc
 #define arm_v7m_cpu_do_interrupt arm_v7m_cpu_do_interrupt_powerpc

qemu/softmmu_template.h

@@ -175,7 +175,7 @@ static inline DATA_TYPE glue(io_read, SUFFIX)(CPUArchState *env,
 
     cpu->mem_io_vaddr = addr;
     memory_region_dispatch_read(mr, physaddr, &val, 1 << SHIFT,
-                                MEMTXATTRS_UNSPECIFIED);
+                                iotlbentry->attrs);
     return (DATA_TYPE)val;
 }
 #endif
@@ -677,7 +677,7 @@ static inline void glue(io_write, SUFFIX)(CPUArchState *env,
     cpu->mem_io_vaddr = addr;
     cpu->mem_io_pc = retaddr;
     memory_region_dispatch_write(mr, physaddr, val, 1 << SHIFT,
-                                 MEMTXATTRS_UNSPECIFIED);
+                                 iotlbentry->attrs);
 }
 
 void helper_le_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val,

qemu/sparc.h

@@ -149,6 +149,7 @@
 #define tlb_flush tlb_flush_sparc
 #define tlb_flush_page tlb_flush_page_sparc
 #define tlb_set_page tlb_set_page_sparc
+#define tlb_set_page_with_attrs tlb_set_page_with_attrs_sparc
 #define arm_translate_init arm_translate_init_sparc
 #define arm_v7m_class_init arm_v7m_class_init_sparc
 #define arm_v7m_cpu_do_interrupt arm_v7m_cpu_do_interrupt_sparc

qemu/sparc64.h

@@ -149,6 +149,7 @@
 #define tlb_flush tlb_flush_sparc64
 #define tlb_flush_page tlb_flush_page_sparc64
 #define tlb_set_page tlb_set_page_sparc64
+#define tlb_set_page_with_attrs tlb_set_page_with_attrs_sparc64
 #define arm_translate_init arm_translate_init_sparc64
 #define arm_v7m_class_init arm_v7m_class_init_sparc64
 #define arm_v7m_cpu_do_interrupt arm_v7m_cpu_do_interrupt_sparc64

qemu/x86_64.h

@@ -149,6 +149,7 @@
 #define tlb_flush tlb_flush_x86_64
 #define tlb_flush_page tlb_flush_page_x86_64
 #define tlb_set_page tlb_set_page_x86_64
+#define tlb_set_page_with_attrs tlb_set_page_with_attrs_x86_64
 #define arm_translate_init arm_translate_init_x86_64
 #define arm_v7m_class_init arm_v7m_class_init_x86_64
 #define arm_v7m_cpu_do_interrupt arm_v7m_cpu_do_interrupt_x86_64